Many devices use integrated power switches to turn power supplies on or off. These switches are used everywhere from hot-swappable racks (industrial), to USB power to mobile devices, like your cellphone. And of course, power switches are important components of DC-to-DC converters. There are good reasons to use integrated switches to turn a load on or off.
First of all they have no moving parts; secondly they are small and they often offer a lot of protective features. The resistances of such load switches should not be a problem — they are easily below 100mΩ and are often under 10mΩ. They can be controlled with a (very low power) electrical signal. What follows focuses on the physical design of an integrated power switch.
The designer of such a switch faces some exciting tasks, including the design of several interacting control loops and a challenging physical layout design. The low resistance is not a given for most IC processes. The metal layers of the IC commonly have sheet resistances in the 80mΩ/sqr. range. The top metal layer may have a much lower sheet resistance, especially when options of “thick top metal” are offered. This may bring Rsheet down below 20mΩ/sqr. How does one make a switch of, say, 10mΩ with these kinds of metal interconnects?
Another main component in the resistance budget is, of course, the Rds_on (on resistance, drain-to-source) of the MOSFET. With few exceptions, NMOS devices are chosen as the actual switching device, because of their smaller size for the same on-resistance compared to PMOS.
The MOSFET on-resistance is often characterized by a figure of merit expressed in ohm-mm2 . For example, an NMOS could have a typical on-resistance of 3mΩ-mm2 . This means that one square mm filled with units of this NMOS has an Rds_on of 3mΩ. This looks like a promising start; however, the on-resistance parameter assumes a minimal number of substrate ties (or none at all).
In order to make the switch robust we want to keep the associated bipolar device turned off at all times. This parasitic bipolar is formed by drain (acting as collector, n-type), substrate (acting as base, p-type) and source (acting as emitter, n-type). Due to the very large width-to-length ratio of the switch FET, we are dealing with a hefty bipolar device, as well. Typical values for the width of the drain/source might need to be 20 centimeters, and the distance between drain and source (channel length, base) might need to be 0.5 micrometers to get the desired results. Once this bipolar transistor turns on, there is no stopping the ensuing destruction, usually seen as fused bond wires after the smoke has cleared.
There are several mechanisms for the bipolar to turn on. Even a slight inductance of wiring connected to the power switch can cause voltage spikes, leading to injection of currents into junctions on the chip, in turn causing triggers for latchup. Coming back to the substrate ties: We need a lot of them to keep the Vbe of the parasitic as close as possible to zero at any time. And we want a good-sized guard ring around the device to collect any latchup-causing currents. After adding all those substrate contacts, guard rings, and other necessary routing, such as gate interconnect and perhaps sense FETs, the Rds_on of the one square millimeter of NMOS is now probably higher than 10mΩ.
In part 2, we will look at the interconnects from the silicon chip to the IC's pins. We will also look at ways to keep the on-resistance, which includes those interconnects, as low as possible.