I am sure you have often heard analog design described as an art. This statement is especially true when dealing with radio frequencies. However, is it true when dealing with analog “baseband” type circuits? The answer is yes!
So why are we discussing analog design as being an art? I believe it is an art to properly understand where and how unwanted energy disturbs circuits, causing them to behave unexpectedly or causing a reduction in performance from the intended targets. To try and attack these types of issues, board and integrated circuit designers use capacitors to filter out the unwanted energy.
The existence of unwanted energy from various sources plagues board design as well as embedded system designs. With this in mind, I would like to focus on embedded systems integrated on silicon substrates. These embedded circuits get their power and signals from the outside world. This interface between these two domains is usually one of the weaknesses in circuit design. I would argue that if, during the design process, currents could be contained inside the embedded system, then interference could be controlled. However, this is not reality, because signals and power must come from external sources outside the embedded system. Therefore, the challenge is controlling the frequency content and energy of these signals. To combat these issues, capacitors are used to filter unwanted energy from signals, power supplies, and references.
In combating this, it is often helpful to use large capacitors with large capacitance reservoirs of charge. This idea of employing a large capacitive reservoir is a great idea, provided the reservoir is capable of discharging in a fast transient environment. This is where the problem lies. All capacitors are not equal in their performance. Using a bigger cap is not always the best answer. Ideally, the capacitor should be sized for the amount of charge needed to supply transient current to the circuit for which the capacitor is filtering or decoupling. Therefore, it is important to know your environment from a frequency perspective (i.e., what frequencies can cause unwanted interference) and power-needs perspective.
Capacitors are never ideal and have distinctive resonance points that limit their useful frequency response capability. Larger caps have the tendency to respond well to DC-type signals whereas smaller value chip caps have a much higher frequency response (see Figure 1). The key is to know your environment and use a combination of smaller capacitors in parallel with the larger capacitors if possible — especially in your board development.
The frequency response curves shown in Figure 1 also exist for embedded capacitors. Typically, the preferred use of caps for filtering supplies and other sources of unwanted energy is on-chip metal-to-metal caps. The problem is that these caps have low capacitance density and result in large areas consumed on the die. Therefore, the other often used option is to use poly-to-poly or MOSFET capacitors. These caps offer more capacitance density but suffer from poorer frequency response and are not as linear. However, with the correct choice of capacitor sizes the effects of reduced frequency performance can somewhat be mitigated.
The unfortunate problem with using poly or MOSFET caps is that the frequency response of the capacitor is not always modeled or is not modeled until an extraction is completed, which means the layout is complete. Therefore, the question is how to estimate the frequency response of the capacitor before the layout is complete. If the models are such that a varactor model exists, then the response can be simulated. However, there are times when no such model exists. Furthermore, the knowledge of how the capacitor behaves over frequency helps the engineer understand the sizes of the capacitor needed before any simulations take place. So what to do? The answer is to develop a model that approximates and provides a trend for the frequency response of the capacitors used.
To develop such a model, I have used a distributed model, as shown in Figure 2 where the total capacitance and series resistance of the MOS cap is distributed such the capacitance C0=C2=1/6 of the total capacitance and C1=2/3 of the total capacitance. The series resistance is broken up in R1=R2=1/2 of the total series resistance (Rt). This model further uses equations based on the MOSVAR model developed to estimate the values of the series resistance. The total series resistance of the MOSVAR model is shown in Figure 3 where Rt=R1&R2 is equal to the combination of Rgsal +Rsub (where the parameters used in this model are pulled directly from the technology files).
When this simplified model is developed, the designer can quickly estimate the affects of how the capacitance behaves over frequency. This enables the designer to quickly choose a capacitance width and length that meets the frequency response needs for the circuit. In addition, for embedded circuit designs, this simple model provides the designer tools needed to determine the size of the capacitor before the capacitor is implemented in silicon. Although the simple model is not completely accurate for the purposes of circuit design and planning of the chip-level integration, the simple model enables more robust system designs.
Briefly, it is important to make a few statements on the assumptions assumed using the MOSVAR model in the development of the frequency response of the capacitor. The model for the capacitor assumes Rend and Rvert ≅ 0 with Rsub as the dominant term. With these assumptions, I can create a simple model where the top plate (Rtop ) and the bottom terminal (Rbot ) for the effective resistance are given on page 12, equation 3.45 of the PSP model for a MOS varactor as:
However, just as important, the assumption that Rac does not contribute is in error, because in heavy accumulation Rac may be a small resistance. This resistance is dependent upon how the transistor is biased. Because the component Rac is dependent on the potential of the bulk to gate as well as other factors such as mobility and accumulation charge, the calculations in the model developed use just an Rsub . This provides a more pessimistic response but provides a trend to work with as the response will only be better.
Shown in Figure 4 is a simple MATLAB simulation of what a model might be used to predict. The use of the model described is implemented in MATLAB code to show when the 3dB rolloff of the capacitance occurs in the model. This enables the design early on in the system design or circuit design to make the appropriate tradeoffs when planning for decoupling capacitor needs.
Do you see the need for such a “back of the envelope” hand estimation model in your company? How do you estimate the correct values for capacitance values pre-layout?
Yes, I agree with the heading or title of this piece. Bigger caps are expensive because they take space. Sure, they can give peace of mind, but if you have solid understanding of the dynamics of your design, do not waste space with bigger cap. Use what is minimally possible!
I think when it comes to industrial applications, there's always a budget constraint to keep the costs low. This makes the designers the pressure to choose the most optimal component that gives the right amount of functionality without driving the cost up. Bigger capacitors would add to cost and unless that's needed, it doesn't seem like an optimal choice.
I would like to thank author here for giving such a catchy tag line, yes bigger is not always better. Bigger capacitor not only add cost but problems too, as it would draw more current and long charging time.
“Use what is minimally possible”
@fasmicro: It is mainly the transients that capacitors should be designed for. The sudden spike of charge can be satiated so that nop-ideal voltage source is not burdened.
Brandt, Thanks for the post. I think when the MOS devices are used as capacitors, one more important parameter is the voltage modelling. Since the capacitor is due to junctions, the capacitor becomes a function of bias voltages applied. The effective capacitor is between Gate and the Substrate, but the voltage from Drain to Source will also be important. If there is a huge delta then the channel may not be uniform, which needs to be modelled.
Brandt,
The model that you have derived here is of a single capacitor and you have considered the distributed RC network for the MOS cap. If we use a lumped model we would never be able to get the effects of zeros (or inductive behaviour).
Is there any way to find how long the channel length is so that the resistance can be increased and we can play with the placement of zeros or there are other more serious consequences for this?
To add little more, we cant have constant potential difference between the terminals, capacitor voltage will degrade continuously.
@Samicksha: Yes, we need to take care of the leakage (may be dielectric leakage or reverse biased junction leakages). A very large resistor across the terminals.
To make it more complex we can add the tempco to the resistor too.
Brandt,
I was looking at the figure 2 distributed RC model and the figure 3 cross sectional view of the device.
I can say that C2 is our intended cap, while the C1 is the Cfringe , what does C0 represent?
Is this model made just to curve fit the expected RC behaviour, which makes sense, but then Figure 3 becomes confusing.
I can say that C2 is our intended cap, while the C1 is the Cfringe , what does C0 represent?
@amrutah, I had similar doubts when I read those equations.I am not sure what C0 stands represents.
Partially, I would agree with amrutah as far as reduction of leakage is concerened. However, there seems to be a better way of achieving that. Would be interesting to know more about reduction of leakage.
It is quite true that continous degradation of the capacotors's voltage is possible by ensuring contant potential diffrence between the terminals as suggested by Samicksha. It even serves as a better option though implementing it in large scale appeasrs tricky though managable.
I think certain situations only require larger capacitors regardless of how great a smaller one might turn out to be. In essence, every application should be handled separately withoput necessarily making unnecessary generalisations.
Generally speaking, big cap needs the bigger space and more cost than small cap. As this blog commented, big cap might not provide the good frequency in some cases. Big cap and small cap should be carefully chosen in the circuit. This blog reminded me of cap's electric characteristic in the board.
>> I think when the MOS devices are used as capacitors, one more important parameter is the voltage modelling.
There are many ways of making capacitors in a CMOS process. What do you think are the main advantages of the MOS type and the ones done with Polysilicon.
@Goafrit:
I agree we have many ways of fabricating a cap on chip. It can be a Poly1-Poly2, or Device cap or Poly1-Metal caps.
The advantages I see is
@amrutah, thanks for sharing the info. I am curious to know when do we use polysilicon capacitors ?
Big cap and small cap should be carefully chosen in the circuit. This blog reminded me of cap's electric characteristic in the board.
@DaeJ, I agree with you. I think this blog really helps us to understand the electric characteristics of the Cap. I think we should understand the frequency behaviour of the circuit before we choose big or small cap.
Bigger capacitors would add to cost and unless that's needed, it doesn't seem like an optimal choice.
@tzubair, it not only adds cost but it also takes up lot of space which will again impact the profit margin. Hence we should to try to choose the capacitors wisely.
The effective capacitor is between Gate and the Substrate, but the voltage from Drain to Source will also be important. If there is a huge delta then the channel may not be uniform, which needs to be modelled.
@amrutah, thanks for sharing this info, I was not aware of dring to source voltage impact on effective capactor . Can we model this behaviour ? Is there any model which takes care of Drain to Source voltage ?
@SachinEE… most of the mosfets are very well modelled and also the VDS is very well modelled when it comes to the channel characteristics. But when it comes to the formation of capacitor and the effective capacitance,I don't know if it's modelled. If someone can throw light on this.
@amrulah: Well its modelled to it but its not functioning as it is.
@SachinEE: Yes we can model this behavior.
@SachinEE: Yes if not it will be a waste indeed.
@SachinEE: Well its always good to have a constant monitoring of the frequency levels. That will help to identify whether to go with the smaller one or the bigger one.
@Sachinee: Is it needed at this juncture ?
>> I agree we have many ways of fabricating a cap on chip. It can be a Poly1-Poly2, or Device cap or Poly1-Metal caps.
When making the selection, consider your process and density per uFarad. Always examine the available area on silicon to direct the type of cap you decide to choose. There are many effects like temperature you must also look into .
>> I am curious to know when do we use polysilicon capacitors ?
When you need high density capacitors. That gives you more values per area of silicon. Of course your process parameters play a role here as well.
>> I think we should understand the frequency behaviour of the circuit before we choose big or small cap.
Technically, besides other factors, that is what the cap is supposed to help. While you can use caps to store charge, the big deal is compensation especially in opamps.
>> Bigger capacitors would add to cost and unless that's needed, it doesn't seem like an optimal choice.
If a designer chooses caps not based on what the circuit needs and ends us using more value than needed, that is a bad designer. There is no sense in using a cap of 2pF when 1.5pF can do the job.
@Dassa.an: Can you please point me to any paper describing this?
@Fasmicro: I agree, the most important factor for me is parasitics and matching, tempco. Since most of these will define the shift in frequency for the oscillators.
To add to what fasmicro suggested, I poly caps match better, density is good, more effective capaticance and does not need a minimum specific voltage at its terminals (unlike the transistor cap, which requires to be biased in order to form channel).