I am sure you have often heard analog design described as an art. This statement is especially true when dealing with radio frequencies. However, is it true when dealing with analog “baseband” type circuits? The answer is yes!
So why are we discussing analog design as being an art? I believe it is an art to properly understand where and how unwanted energy disturbs circuits, causing them to behave unexpectedly or causing a reduction in performance from the intended targets. To try and attack these types of issues, board and integrated circuit designers use capacitors to filter out the unwanted energy.
The existence of unwanted energy from various sources plagues board design as well as embedded system designs. With this in mind, I would like to focus on embedded systems integrated on silicon substrates. These embedded circuits get their power and signals from the outside world. This interface between these two domains is usually one of the weaknesses in circuit design. I would argue that if, during the design process, currents could be contained inside the embedded system, then interference could be controlled. However, this is not reality, because signals and power must come from external sources outside the embedded system. Therefore, the challenge is controlling the frequency content and energy of these signals. To combat these issues, capacitors are used to filter unwanted energy from signals, power supplies, and references.
In combating this, it is often helpful to use large capacitors with large capacitance reservoirs of charge. This idea of employing a large capacitive reservoir is a great idea, provided the reservoir is capable of discharging in a fast transient environment. This is where the problem lies. All capacitors are not equal in their performance. Using a bigger cap is not always the best answer. Ideally, the capacitor should be sized for the amount of charge needed to supply transient current to the circuit for which the capacitor is filtering or decoupling. Therefore, it is important to know your environment from a frequency perspective (i.e., what frequencies can cause unwanted interference) and power-needs perspective.
Capacitors are never ideal and have distinctive resonance points that limit their useful frequency response capability. Larger caps have the tendency to respond well to DC-type signals whereas smaller value chip caps have a much higher frequency response (see Figure 1). The key is to know your environment and use a combination of smaller capacitors in parallel with the larger capacitors if possible — especially in your board development.
The frequency response curves shown in Figure 1 also exist for embedded capacitors. Typically, the preferred use of caps for filtering supplies and other sources of unwanted energy is on-chip metal-to-metal caps. The problem is that these caps have low capacitance density and result in large areas consumed on the die. Therefore, the other often used option is to use poly-to-poly or MOSFET capacitors. These caps offer more capacitance density but suffer from poorer frequency response and are not as linear. However, with the correct choice of capacitor sizes the effects of reduced frequency performance can somewhat be mitigated.
The unfortunate problem with using poly or MOSFET caps is that the frequency response of the capacitor is not always modeled or is not modeled until an extraction is completed, which means the layout is complete. Therefore, the question is how to estimate the frequency response of the capacitor before the layout is complete. If the models are such that a varactor model exists, then the response can be simulated. However, there are times when no such model exists. Furthermore, the knowledge of how the capacitor behaves over frequency helps the engineer understand the sizes of the capacitor needed before any simulations take place. So what to do? The answer is to develop a model that approximates and provides a trend for the frequency response of the capacitors used.
To develop such a model, I have used a distributed model, as shown in Figure 2 where the total capacitance and series resistance of the MOS cap is distributed such the capacitance C0=C2=1/6 of the total capacitance and C1=2/3 of the total capacitance. The series resistance is broken up in R1=R2=1/2 of the total series resistance (Rt). This model further uses equations based on the MOSVAR model developed to estimate the values of the series resistance. The total series resistance of the MOSVAR model is shown in Figure 3 where Rt=R1&R2 is equal to the combination of Rgsal +Rsub (where the parameters used in this model are pulled directly from the technology files).
When this simplified model is developed, the designer can quickly estimate the affects of how the capacitance behaves over frequency. This enables the designer to quickly choose a capacitance width and length that meets the frequency response needs for the circuit. In addition, for embedded circuit designs, this simple model provides the designer tools needed to determine the size of the capacitor before the capacitor is implemented in silicon. Although the simple model is not completely accurate for the purposes of circuit design and planning of the chip-level integration, the simple model enables more robust system designs.
Briefly, it is important to make a few statements on the assumptions assumed using the MOSVAR model in the development of the frequency response of the capacitor. The model for the capacitor assumes Rend and Rvert ≅ 0 with Rsub as the dominant term. With these assumptions, I can create a simple model where the top plate (Rtop ) and the bottom terminal (Rbot ) for the effective resistance are given on page 12, equation 3.45 of the PSP model for a MOS varactor as:
However, just as important, the assumption that Rac does not contribute is in error, because in heavy accumulation Rac may be a small resistance. This resistance is dependent upon how the transistor is biased. Because the component Rac is dependent on the potential of the bulk to gate as well as other factors such as mobility and accumulation charge, the calculations in the model developed use just an Rsub . This provides a more pessimistic response but provides a trend to work with as the response will only be better.
Shown in Figure 4 is a simple MATLAB simulation of what a model might be used to predict. The use of the model described is implemented in MATLAB code to show when the 3dB rolloff of the capacitance occurs in the model. This enables the design early on in the system design or circuit design to make the appropriate tradeoffs when planning for decoupling capacitor needs.
Do you see the need for such a “back of the envelope” hand estimation model in your company? How do you estimate the correct values for capacitance values pre-layout?