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Chip design converges with packaging and PCB in SoC era

The previous articles in this series showed how the successful integration of IP—especially analog/RF, but digital as well—is essentially pre-determined by the practices of the chip development team from the very beginning of a design effort. The issues that emerge at chip, package and PCB levels during IP integration interact across all three domains in the form of signal integrity (SI) and power integrity (PI) problems.

Signal integrity issues include timing effects—jitter originating from compromised edge rates that worsen with rising frequency—and amplitude effects like electromagnetic interference (EMI), including crosstalk and harmonics at both low and high frequency. Power integrity issues encompass switching noise and crosstalk, which must be managed dynamically so that neither functionality nor performance are compromised.

It’s a challenging situation because of the need to maintain clean power levels and noise margins in the face of Vdd declining in step with deeper submicron nodes. One cannot fail to notice the many commonalities between these problems as well as the methods employed to curtail them at all three levels of system design and integration.

Figure 1 An illustration of signal and power integrity issues, their origins, and methods of resolution. Source: P2F Semi

What has followed upon the realization that IP integration problems are due to design methods which do not treat chip, package and PCB design as a comprehensive whole is an effort to develop a methodology that can successfully confront this multivariate mess. From this has arisen the concept of a power distribution network, or PDN.

Power distribution network

The basic concept is centered on a common and consistent impedance Z which can serve as a design requirement for the chip, package, and PBC. Using the generic formula Z = delta V (power supply noise)/I, the Z parameter can be estimated from the transistor current draw I, which is assumed to be a constant. This serves as an upper limit for all three levels of the system across the full range of operating frequency.

Z will vary across all three levels based on individual factors of R, C, L and operating frequency. The upper limit will be dominated by R and L, while the lower by C at any given resonant frequency. What the RLC values are at each level will depend on that level’s ground plane, use and dimensions of bulk or decoupling capacitors, pins, traces, and so forth.

The commonalities in EMI sources between the three hardware levels become glaringly obvious with PDN methodology. Some examples of these universal problems and guidelines for their remedies include:

  • DC power and signals follow the path of least resistance; AC follows the path of least impedance.
  • Current return paths with discontinuities are a common source of EMI. These are managed frequently with decoupling caps, though insulating materials composed of thin or high permittivity dielectrics are used as well.
  • Coupling can be both capacitive and inductive, and worsens with higher frequency. Using the shortest possible traces to a ground reference is imperative.
  • Ground planes in both packages and PCBs shield signal layers from crosstalk and block noise from EMI. However, both levels are at risk of frequency-dependent resonances between ground planes and power planes and will almost certainly need decoupling.
  • Through silicon vias (TSVs) and through mold vias (TMVs) in packaging have become a potential source of crosstalk at all three levels. Proper spacing, scattering ground vias between signal vias, differential signaling and shortest distance to ground references are all used to mitigate the problem. Fixes for this issue are quite specific to chip design—particularly for 2.5/3D IC—and the problem is receiving a lot of attention.
  • Heavy use of decoupling caps will affect floorplanning, layout, and design choices at all three levels with associated negative implications to cost. However, current changes from inductive parasitics will be dependent on current draw at the chip level and can instigate more current draw from an on-chip voltage regulator—a highly undesirable event, as on-chip regulators are a source of parasitic capacitance. Decoupling caps serve an essential role here as ‘rechargeable batteries’ that even out current flows. Thus, using decoupling caps is an inescapable reality.

We can clearly discern from the above information the growing number of interdependencies between successful chip, package, and PCB design.

From chip to package to PCB

Chip suppliers discovered some time ago that building a demo board for a chip is vastly simpler than developing a full-blown system implementation. However, in the SoC era, semiconductor vendors are beginning to realize that their own field is rapidly converging with packaging and PCB. As we can see now quite clearly, this convergence is driven by the need to integrate in silicon both digital and analog IP of extraordinary complexity and functionality. Stated differently: in order to properly integrate system IP in silicon, chip developers must, in effect, become system developers.

This is turning into a requirement for chip design teams to expand their skills in order to encompass co-development at the chip, package and board level during the full modeling, design, simulation, and verification cycle. EDA vendors are attempting to respond to this emerging need by offering new tools and flows for their incorporation into a chip development toolchain. There are no clear winners amongst these offerings as of yet, but the rapidity with which this field is growing is starkly evident. One very comprehensive methodology for chip/package/PCB codesign including front and back end is illustrated in Figure 2.

Figure 2 The illustration highlights a comprehensive chip, package, and PCB co-design methodology. Source: P2F Semi

An essential addition to the above flow would be to incorporate prototyping of each level at successive layers of abstraction, going from high abstraction—black box modeling—to medium abstraction—trial layouts and coarse placement and routing of more complete chip blocks in conjunction with physical prototyping of package and PCB, and finally to low or zero levels of abstraction as logic design is completed. Here, the SoC design solidifies and physical design and integration concerns predominate. By engaging in co-design between all three levels dynamically from the very beginning, IP integration issues can be addressed through cycles of planning and optimization before final tapeout and difficulties such as schedule slips and iterative rework can be avoided.

Regardless of the effectiveness of any given EDA tool or flow, it is abundantly clear at this point that it’s no longer sufficient to design a chip and integrate its digital and analog IP, then optimize die placement in a chosen package and in turn optimize the placement of the device on a multi-layer PCB with successive stages completed serially and in relative isolation. Engaging each level independently will ensure significant cost overruns, schedule delays, and work cycles wasted on re-engineering.

The integration of semiconductor digital and analog IP can only be timely, efficient and completely successful when the chip design team accounts for the ‘vertical’ dimension of the SoC and includes detailed packaging and PCB parameters in design, simulation and verification flows, treating the three levels as one system. The SoC development is no longer just a silicon-based discipline. In order to properly manifest the functional richness of SoCs filled with digital, analog, RF and mixed-signal IP blocks, chip design teams will from now on be required to further encroach on the engineering territory of systems houses, moving beyond the logical level and into the physical as well.

Kedar Patankar, chief technology officer (CTO) at P2F Semi, is a semiconductor industry veteran with 23 years of experience in design, development, and customer relations.

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