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Analog Angle Article

Choosing an ADC: when the “D” becomes as important as the “A”

When you're looking at high-performance analog/digital converters (ADC or A/D converter), it's traditional to focus primarily on the analog-conversion specifications including resolution, speed, INL, DNL, SFDR, ENOB, and THD, and worry less about the digital side of the converter. In fact, up to a few years ago, your options for digital output format and structure were fairly limited: parallel or serial output; straight binary or twos complement data; and TTL or CMOS levels. Then came emitter-coupled logic, ECL (relatively uncommon these days) and serial LVDS (quite common now).

But things really have changed. In a recent discussion with Alison Steer, Product Marketing Manager, and Steve Logan, Product Marketing Engineer at Linear Technology Corp (LTC) about their LTC2261 ultralow-power 14 bit, 125 Msps ADC, much of the discussion was about the many user-programmable options for the digital output, set via an SPI port. Among the choices are:

  • Full rate CMOS using 14 data lines
  • Double data rate (DDR) CMOS, 7 data lines
  • DDR LVDS, 14 data lines, for reduced digital noise
  • Straight binary or twos complement data coding

But the choices don't stop there. You also have these:

  • Selectable LVDS output current (1.75 to 4.5 mA), to match output current to the load, while minimizing power dissipation
  • Internal 100-ohm resistors which you can switch in, to absorb reflections due to impedance mismatch at the receiver
  • A data randomizer which scrambles the output bits via an exclusive-OR circuit, to reduce noise coupling from major signal transitions and improve SFDR (the data receiver, of course, must do a reverse XOR to unscramble them) [Note that some other ADCs support a new JEDEC standard for 8B/10B encoding of the data, thus adding another level of sophistication and complexity, see Reference below.]
  • And programmable timing (via phase shifting) of the output clock, to precisely match the converter timing to various FPGAs and digital down converters (DDC)

What accounts for this emphasis on the digital outputs? Mostly, it's the increasing use of high-speed converters and their requisite outputs, along with lower voltage levels, all of which brings additional concern about overall signal integrity and outright corruption of the digital bits (yes, it happens), as well as the problems which high-speed signals cause in adjacent analog and digital signals.

And if you think that a converter just has to take an analog input and produce a corresponding digital output: even that is no longer enough. The LTC2261 can also be programmed to produce specific “test pattern” outputs of all zeroes; all ones; checkerboard one/zero (10101010. . . .); and alternating pattern (a string of 1s, a string of 0s).

Sure, it's a lot to ask of an ADC, but there's it's a trend that will accelerate as analog and mixed-signal ICs get faster, lower power, and increasingly embedded in mainstream products. But maybe, just a little, I miss the “plain-Jane, no extras, no options” ADCs of the past, that didn't require so many design decisions!

Reference

  • “Understand the new JESD204 standard for single-transmission-pair, serial communication from your analog/digital converter,” by Clarence Mayott, Planet Analog , June 12, 2008, click here

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