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Choosing and Using Bypass Capacitors (Part 3 of 3)

(You can read Part 1 by clicking here)

Bypass Capacitor Application Examples
So far we have presented the main issues involved in designing optimum bypass networks. However, each circuit and each system will have specific demands that need to be addressed. The trade-offs involved in each particular instance can frustrate the best designers. Therefore, four different application examples are presented here. These examples have been chosen as representative of low current/low frequency, low current/high frequency, high current/low frequency and high current/high frequency systems. Table 5 shows the chosen circuits.


Table 5: Application examples for bypass consideration

Example 1 (low current/low frequency): Real-time clock-calendar with EEPROM
The block diagram of our first example, the ISL12026 is shown in Figure 12 . This system has three separate areas that require special bypass attention. Please note that this discussion assumes the use of an 8-pin SOIC package.


Figure 12: Block diagram of Real-time Clock-Calendar with EEPROM circuit
(Click to Enlarge Image)

The first area of concern is the EEPROM program array, Figure 13 . To handle programming glitches, two capacitors should be placed in parallel at the supply pin, pin 8 of the SOIC. First, use a small capacitor (0.01 uF suggested) to handle digital switching transients. Second, use a large capacitor (1 uF suggested) to compensate for current droops on the power supply. These two capacitors should be placed in parallel between the supply node and ground.


Figure 13: Suggested layout for ISL12026.

Secondly, the crystal (X1) needs to be placed as close to the device as possible to eliminate high frequency coupling, Figure 14 . If these traces are not minimized, additional bypass capacitors will be needed on the supply to remove any coupled signals.


Figure 14: Suggested layout for ISL12026 in regards to crystal placement

This device allows for battery back-up. That feature is designed with a hand-off between line and battery power. Within this hand-off region, there is an overlap where both supplies are connected to the device. This supply overlap may cause switching transients. Adding a 0.1 uF capacitor in parallel with the battery will minimize these transients.

Example 2 (low current/high frequency): voltage reference
The block diagram of our second example uses the ISL6002 to provide a voltage reference. Although voltage references are typically considered low frequency devices, they must be bypassed over the entire bandwidth of the system they are serving. Figure 15 shows the ISL6002 voltage reference regulating the supply of a high speed ADC.


Figure 15: Voltage regulator and ADC block diagram
(Click to Enlarge Image)

In this example, the input to the voltage regulator is bypassed with the standard two-capacitor fashion previously discussed in the “sizing” section. The output of the regulator is also bypassed to provide a low-impedance supply to the ADC.

If the ADC (or any other load) has a large input capacitance, you may need to add an R-C to absorb switching transients and reduce ringing (Figure 16 ).


Figure 16: Voltage regulator bypassing with large capacitive load
(Click to Enlarge Image)

Example 3 (high current/low frequency): DC/DC converter
The simplified block diagram of a DC/DC converter is shown in Figure 17 . A pulse-width modulator controls switches to manipulate currents through large inductors to create the desired output voltage.


Figure 17: Simplified block diagram of a DC/DC converter
(Click to Enlarge Image)

The DC/DC converter circuit can be further simplified when considering only one of the switching states (Figure 18 ).


Figure 18: Active DC/DC converter circuitry in one switch configuration
(Click to Enlarge Image)

Typically, a lot of attention is paid to choosing the inductor. The quality of the capacitor is often taken for granted. The circuit from Figure 18 is expanded to include the parasitics of the capacitor (Figure 19 ).


Figure 19: Simplified DC-DC converter with capacitor parasitics

The effect of these parasitics is more apparent because of the large current through them. A summary is provided by the following equation:




The output voltage will exhibit a ripple proportional to the amount of parasitic resistance (ESR) and parasitic inductance (ESL) associated with the capacitor, Co. The information in Table 2 allows the designer to choose the best capacitor for the performance of their DC/DC converter.

Of course, this circuit also needs bypassing at both the input and output as in the voltage regulator example. Layout is critical and multiple devices are commonly crowded around both supply terminals.

Example 4 (high current/high frequency): DSL amplifier
A DSL amplifier must handle the large currents needed to drive communication lines at high speeds. Many of the same techniques reappear in this example. Again, bypass the amplifier as close to the supply pin(s) as possible. Any extra resistance (ESR) in the bypass path lowers the quality factor (Q). Likewise, any extra series inductance (ESL) lowers the self-resonant frequency of the bypass leg, possibly dipping into the bandwidth of the system. Note that ESR and ESL are not only generated by the bypass capacitors, they also appear in traces as well as via construction.

As shown in Example 2, it is common to use at least two bypass capacitors in parallel. Two caps reside on the positive and negative supply. The smaller value cap appears in a smaller package and is placed closer to the device. Figure 20 presents the bypass capacitors C1-C4 of the ISL1557.


Figure 20: Layout of high-speed amplifier highlighting placement of bypass capacitors.

When the circuit operates at especially high frequencies, a third cap (smaller than the other two in size and value) may also be added. The smallest capacitor should be placed closest to the supply pin to minimize parasitics. As the sizes of the capacitor increase, their respective distances from the supply pins can also increase.

Many designers like to add a series resistance to bypass capacitors to lower the quality factor (Q) of the bypass network. The effect is graphed in Figure 21 and Figure 22 using a simple, two-capacitor bypass network.


Figure 21: Frequency response of two scaled capacitors in parallel (for reference)
(Click to Enlarge Image)


Figure 22: Frequency response of two scaled capacitors in parallel. One capacitor has been “de-qued” by an additional series resistance.
(Click to Enlarge Image)

Adding a series resistance does indeed flatten the impedance versus frequency of the bypass network, but does not lower the overall impedance at any frequency. It is not recommended unless an especially flat frequency response is needed.

Summary
An introduction and overview of bypass capacitor and bypass techniques has been presented. Two main issues have been identified: high currents and high frequencies. Bypass capacitors must by chosen properly to handle the size and speed of transients. Parasitics need to be minimized. Many new specialized products are available for this very function (OSCON or X2Y). The most common solutions, however, use multilayer ceramic chips caps.

No matter which capacitor is chosen, layout is critical for quality bypassing. Bypass capacitors must be placed as close to the pins on the IC as possible to minimize additional ESR and ESL.

Finally, a number of applications examples were discussed. Their specifics provide insight into practical situations. One last resource is also provided (Table 6 ) which organizes other common circuits into our current/frequency matrix. Please use this guide to identify major issues and confidently design better bypass networks.


Table 6: Other application circuits with similar current and frequency issues
(Click to Enlarge Image)

About the authors
Mike Wong is the VP of application engineering focusing on high speed analog and mixed signal applications at Intersil Corp. He has previously worked on power supplies at ASTEC. He has a BSEE from the University of California at Davis.

Tamara (Papalias) Schmitz is a principal application engineer for analog applications at Intersil Corp. She is also a full-time professor of Electrical Engineering at San Jose State University. She has a BSEE, MSEE and PhD in RF CMOS design from Stanford University.

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