Hillsboro, Ore.—Lattice Semiconductor's ispClock5316 and ispClock5320 clock distribution ICs, extensions to the company's ispClock5300S family of in-system programmable, zero-delay, single-ended clock buffers, are 16- and 20-output devices for advanced microprocessor system applications.
“Our ispClock5300S family provides ideal low-cost clock distribution devices for any microprocessor-based system,” said Stan Kopec, corporate vice president of marketing. “Using a single chip to fan out all clocks from a single source avoids timing issues due to cascading. With these new devices, the ispClock5300S family now can address all clock distribution applications which require zero delay buffers and fan-out buffers with up to 20 outputs.”
The ispClock5300S devices support four operating configurations, including the zero-delay buffer mode, combined zero-delay and non-zero-delay fan-out mode, dual fan-out buffer mode, and fan-out buffer mode with output dividers.
The ispClock5300S devices use three, 5-bit on-chip output counters to generate up to 3 clocking frequencies derived from one reference. Output clock frequencies can range up to 267 MHz. The universal fan-out buffer has a maximum pin-to-pin skew of 100 ps, regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 70 ps and the period jitter is less than 12 ps (rms). The output skew of each clock net relative to the reference input can be controlled further in delay increments of 156 ps (lead or lag) to compensate for differences in circuit board clock network trace length.
The universal fan-out buffers also support a wide variety of popular single-ended logic standards (LVCMOS, LVTTL, HSTL, SSTL) at a variety of voltage levels on the outputs, while reference inputs support single-ended or differential inputs. The input termination and output impedance of each output can be individually tuned to match each trace impedance.
The Lattice Windows-based mixed-signal software design tool, PAC-Designer Version 4.9, provides comprehensive support for all ispClock5300S devices. Design configurations can be downloaded quickly via the PC parallel port. This version of the PAC-Designer software can be downloaded free; click here.
Clock here for information on the ispClock family of devices. The ispClock5316S and ispClock5320S are priced fromt $3.80 and $4.10, respectively, in 10k quantities. Both devices are available immediately in a pin compatible 64-pin TQFP package in both commercial (0 to +70°C) and industrial (-40 to +85°C) temperature grades. PAC-SystemCLK5312S evaluation kits can be used with all family members (presently five) and are available through authorized Lattice distributors or on the Lattice website for $295.
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