Clock supports multiple distribution networks

Hillsboro, Ore. — Lattice Semiconductor Corp. unveiled the first member of a family of in-system programmable, zero-delay, single-ended universal buffer devices with four operating configurations to support the implementation of multiple clock distribution networks.

The E2CMOS -based ispClock5300S devices support programmable clock skew, termination and interface standard support. The four operating configurations include zero-delay buffer mode, combined zero-delay and non-zero-delay fan-out mode, dual fan-out buffer mode and fan-out buffer with output dividers.

“Our ispClock5300S device family provides a standard clock distribution solution across multiple designs,” said Stan Kopec, Lattice's corporate vice president of marketing. “Traditionally, designers have resorted to using unique Zero-Delay Buffer ICs, Fan-out Buffer ICs and Logic Translator ICs for each clock network design. The ispClock5300S family allows each pin to be configured for the necessary functions individually, resulting in a simple programmable solution that can be customized to suit the design requirements of each circuit board,” he said.

The ispClock5300S devices use three 5-bit on-chip output counters to provide the generation of up to three clocking frequencies derived from one reference. Output clock frequencies can range up to 267 MHz. The high-performance universal fan-out buffer has a maximum pin-to-pin skew of 100 picoseconds, regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 70 ps and the period jitter is less than 12 ps (rms). The output skew of each clock net relative to the reference input can be controlled further in delay increments of 156 ps (lead or lag) to compensate for differences in circuit board clock network trace length.

The universal fan-out buffers also support a wide variety of single-ended logic standards (LVCMOS, LVTTL, HSTL, SSTL) at a variety of voltage levels on the outputs, while reference inputs support single-ended or differential inputs. The input termination and output impedance of each output can be individually tuned to match each trace impedance.

The ispClock5308 (8 output device) and ispClock5304 (4 output device) are expected to be introduced in the second half of 2006.

The first device, the 12-output ispClock5312S, is available in a 48-pin TQFP package, in both commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature grades.

See related block diagram

Pricing starts at $3.00 each for the ispClock5312S in 10,000-piece quantities. Click here for the ispClock5300S family data sheet.

Lattice Semiconductor , 1-503-268-8000,

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