Wireless infrastructure, broadband and instrumentation applications generally require very high performance clocking circuits. The primary components being clocked in these systems are high speed data converters. There are several key performance metrics required for these clock circuits such as low phase noise and jitter, accurate frequency translation and jitter filtering capability. This article will discuss the clocking technologies required.
Basestation transceivers, broadband modems and high-end instrumentation usually require analog-to-digital converters (ADCs) and/or digital-to-analog converters (DACs) with high dynamic range, high sampling rates, or both.
The requirements on a given converter will be determined by the overall system specifications and architecture. The spectral purity of the sampling clock supplied often has a significant impact on the performance achieved.
For example, consider the wireless transceiver circuit diagram shown in Figure 1. The clock generator provides clocks for the ADCs and DACs, and also distributes clock signals to several of the other circuit blocks.
Figure 1.Transceiver block diagram
A key metric for ADCs used in radio receivers is Signal to Noise ratio (SNR). This will impact how accurately an ADC can sample signals. Ideally an ADC should be able to convert small analog input signals into accurate digital representations with a high degree of resolution. In radio terms, an ADC's SNR will determine the Minimum Detectable Signal (MDS).
Theoretical SNR based on the quantization noise for an N bit converter is given by:
Equation 1: SNR = 6.02(N) + 1.8db
So for a 14bit converter the best achievable SNR would be about 86db.
In Intermediate Frequency (IF) sampling architectures, such as that shown in Figure 1, the requirements on clock jitter can be stringent. In fact, the quality of the clock provided to the ADC is often the limiting factor in the system SNR (Equation 2).
Equation 2: ADC SNR= 20log (2πfanalog tclock-jitter ) db
This defines the relationship between broadband jitter on the sampling clock and the maximum SNR due to that jitter for a given analog input frequency. For example, for a 170MHz sampling clock with broadband jitter of 275f, the SNR can be no better than approximately 70.65db.
In practice, other noise mechanisms within the ADC generally limit the SNR to values below the theoretical level or quantization noise (Equation 1). This internal noise is due to device thermal noise in the analog signal path and the sampling clock path. Device noise in the sampling clock path effectively gets converted to phase modulated noise referred to as aperture jitter. This behaves just like jitter on an externally applied clock and follows the relationship of Equation 2, with the aperture jitter (taperture-jitter ) replacing clock jitter (tclock-jitter ). Equation 1 shows that SNR degrades as sampled IF frequency (fanalog ) increases.
The relationship between the spectral purity of the external clock and achievable ADC SNR can be illustrated by the following set of lab measurements. Figure 2 shows a FFT (fast Fourier transform) for a 14bit ADC sampling an IF frequency of 170MHz. The resulting measured SNR relative to a full-scale input signal, labeled as SNRFS on the plot legend, is 76db. This agrees with the ADC data sheet1 .
Figure 2: FFT for 14 bit ADC. Analog Input Frequency=170MHz, Clock frequency=122.88MHz. SNRFS=76db
Now we will use a clocking IC with an internal VCO that is suitable for practical transceiver card clocking applications. To estimate the impact this clock signal will have on the ADC performance we can first measure the phase noise of the clock circuit (see Figure 3).
Figure 3: Phase Noise of Clocking IC at 122.88MHz
We can use the following equation to convert the phase noise to time jitter over a given frequency range.
The equation integrates the phase errors over a frequency range of interest and converts from an integrated radian error relative to 2π into a root mean squared time error.
By applying the phase noise data of Figure 3 to Equation 3, over a frequency range of 50kHz to 61MHz, a jitter value of 230fs is obtained. The frequency range of 50kHz to 61MHz is used to correspond to the effective FFT measurement range that will be used to check the estimate of the impact of jitter on the measured SNR. The 50kHz low end is due to the effective bin spacing for the FFT and the 61MHz high end is the ADC Nyquist sampling frequency.
Applying this calculated jitter of 230fs to Equation 1 yields an SNR value of 72.2db.
However, the actual achieved SNR will be due to the composite effect of this jitter and inherent ADC noise. Applying a root sum square2 addition of the SNR of the FFT in Figure 2, (76db) and the estimate due to the clock jitter (72.2db) yields a composite SNR of 70.68db.
To check this estimate, the corresponding ADC FFT using the clocking IC as the sampling clock is shown in Figure 4.
Figure 4: Figure 2: FFT for 14bit ADC using clocking IC. Analog Input Frequency=170MHz, Clock frequency=122.88MHz. SNRFS=70.75db
The SNR achieved is close to the estimate based on the clocking IC jitter and demonstrates the criticality of clock jitter on ADC performance. While the above discussion is focused on ADCs, a high jitter sampling clock similarly degrades the noise floor and SNR of a DAC.
The broadband jitter of the sampling clock is not the only aspect of the sampling clock spectral purity that needs to be considered. The “close-in” phase noise3 also impacts system performance.
While close-in phase noise impacts the SNR slightly, the more significant impact comes from phase noise bleeding over from adjacent channel signals that can distort a “desired” signal. This effect is similar to the reciprocal mixing effects of phase noise found in analog mixing processes. The encoding process of a converter essentially replicates a mixing process. The encode clock and analog input signals are multiplied together in the time domain. This results in the familiar convolution in the frequency domain.
The result is that any phase noise skirt on the encode clock, as shown in Figure 5, will be replicated on the sampled input signals. The relative phase noise with respect to each carriers' amplitude will be modified based on the frequency ratio between the encode rate and the sampled signal. A problem arises when a strong adjacent channel signal's phase noise skirt extends into the channel of a weak desired channel, distorting it. This effect is shown in the FFT's of Figure 6. In this plot, a FFT of an ADC sampling a small desired signal with a large adjacent blocker for the clean clock condition and high phase noise condition are overlaid. It can be seen that the phase noise skirt of the clock is replicated on the blocker and extends into the band of the desired signal. The phase noise frequency offset of concern can extend from 10's of kHz to several MHz, depending on the modulation standard being employed.
Figure 5: Spectrum analyzer plot of encode with high phase noise superimposed on plot of a clean clock
Figure 6: Phase noise of blocker extending into “desired” signals band
Sampling clock phase noise effects in DAC's are usually manifested as degradation in the error vector magnitude (EVM) of the modulated signal. For a given modulation scheme, high phase noise effectively smears the constellation points, degrading EVM and potentially raising the bit error rate. This is shown in the 16 QAM constellations plots shown in Figure 7. Figure 7(a) shows the constellation for a clean clock condition. Figure 7(b) shows the effect of the high phase noise clock on the constellation. The phase noise in effect rotates the effective phase of the constellation points, reducing the noise margin between adjacent points. It should be noted that wide band phase noise and jitter can also degrade EVM. In applications where bandpass filtering is used at the DAC output, the primary concern is on the close-in phase noise.
Figure 7: (a) 16 QAM constellation for clean clock. F (b) Impact on constellation of clock with high phase noise.
The spectral purity of the clock is a key aspect of the transceiver clocking solution, but there are several other functions that the clocking system is expected to provide as well.
Referring back to Figure 1, the transceiver has multiple receive channels, each requiring separate ADC. In some cases multiple DAC channels are also used. Additional clock channels may be required to provide clocks to ADCs used for digital pre-distortion, FPGA's or baseband ASIC chips.
The DAC and ADC encode rates are typically different from each other. The FPGA and baseband components may also require different frequencies. A spectrally pure main clock signal needs to be distributed separately to each channel, divided down to the required frequency for that channel and then converted to the appropriate output signal format. Output signals on a single transceiver card often contain a mix of LVPECL, LVDS and CMOS formats. Tight skew is often required between channels in order to limit delay variation on printed circuit board layouts. In some cases injecting a delay or phase offset between two clocks is necessary. This might be required between a converter sampling clock and the clock used to latch the ADC output data into a baseband chip.
Channel to channel coupling is a concern in these systems. DAC and ADC clocks usually operate at different frequencies. Channel to channel coupling, or clock feed through between channels, can result in undesired spurious tones on a sampling clock. If the mixing occurs at the encode input, the issues can sometimes be alleviated by offsetting in time the edges of the primary and the ingress clock. Being able to adjust the delay of each clock can be an advantageous feature of the clock system.
To minimize system downtime, the clocking system should provide “back-up” functionality in case the input reference fails. This is achieved by adding a second reference input that can be switched to in the event the primary reference fails. In the case where both the primary and secondary clocks fail, another layer of functional protection referred to as “Holdover”, can be implemented. In Holdover, the clock system enters a mode where it maintains the clock frequency prior to the input failure for as long as possible. For transceiver systems the Holdover mode is not intended to keep the transceiver operating at its normal performance level, but rather to maintain sufficient clocking functionality so that the appropriate system alarms can be generated to initiate system repair.
(1) AD9445: 14Bit 125MSPS, IF Sampling ADC
(2) RSS = 10 x log (10–SNR/10 + 10 –SNR2/10 )
(3) Sampled Systems and the effects of Clock Phase Noise and Jitter. Analog Devices Application note AN-756 by Brad Brannon
David Brandon is Applications Engineer and David Crook is Product Line Manager for the Clocks and Signal Synthesis division, Analog Devices
For more information on high performance clocking of data converters, visit www.analog.com
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