The first article in this series titled “The common silicon issues in analog IP integration” focused on system-on-chip (SoC) design issues related to incorporating analog IP. Here we begin expanding the chip design team’s sphere in earnest by looking at packaging and PCB issues that impinge on the success of SoC development.
The package considerations
Capacitive coupling is a well-known problem area in SoC design and can be dealt with at the silicon level, but that alone is no longer sufficient as it also manifests itself in packaging. Coupling can also be observed between signal traces—whether or not both are active—and can even come from the power bus.
The different voltage and current levels of RF, analog and digital circuits are to blame. One frequently observed problem is analog/RF circuits becoming a source of EMI for digital blocks, causing intermodulation with frequency summing and harmonics at both low and high frequencies. Sharing package ground and power planes between analog/RF and digital blocks can expose analog circuitry to digital switching noise, major current spikes, and coupling thru poorly implemented return paths. Just as hazardous is tying analog and digital ground pins together, as it risks forming a loop antenna that will both attract and generate noise.
Not all remedies to these difficulties demand exotic approaches. Sound design practices from the past can still work well, such as avoiding current loops by simply remembering to keep source and return paths physically close. But package engineers have had to become quite creative in finding solutions to other SoC-caused problems.
Besides offering embedded decoupling capacitors, some packages have included native inductors as decoupling components to save on space.
Figure 1 The diagram showing a cross sectional flip chip BGA package. Source: P2F Semi
The most cutting-edge work in packaging today, though, is the increasing proliferation of multi-chip vehicles: system in package (SiP), wafer scale integration, and especially, 2.5D/3D IC. Rather than integrating all functions on a single chip, die can be specialized as analog, digital or memory modules and then stacked with thru-silicon vias (TSV), providing connectivity between metal stacks and interposers and aggregating signal and ground pins to interface with package balls and PCB. With the appropriate design rules for TSV distancing and signal/ground distribution, 2.5/3D IC goes a long way toward resolving many signal integrity (SI) and power integrity (PI) issues for ultra-deep-submicron SoC.
2.5/3D IC is still a tiny fraction of the overall semiconductor market, perhaps 2% to 3%. It is, however, a segment that is growing energetically, and might triple in size over the next five to six years. Nonetheless, a multi-chip approach is clearly not appropriate for all chips, as the engineering effort, testing burden and overall design and manufacturing costs are still daunting for all but the very high unit volume segment of the semiconductor market. This technology is still developing aggressively and cannot yet be considered mature.
The PCB issues
There are many parallels between SoC-caused issues in packaging and PCBs. But despite the physical distance between a chip and a circuit board and the much larger size of circuit boards compared to chips or their packages, the problem set is in some ways rather worse.
Basic electrical issues can be more noticeable in PCBs—dielectric loss, dissipation factor and skin effect, for a few. The latter two are particularly impacted adversely by the rising frequencies of digital circuits. These high Fmax blocks create the similar ground plane modulation problems seen in packaging from massive current dumps that destabilize the ground reference for analog circuitry. Going hand in hand with high frequency, data rates in many gigabit channels are also creating more severe crosstalk and inter-symbol interference (ISI) problems.
The regularly different Vdd for analog/RF and digital blocks also contribute to EMI problems for both kinds of circuits—again paralleling the kinds of problems observed at the package level. Even clock signals can become a source of EMI because of their frequency and edge rate.
Figure 2 A cross section of a multi-layer PCB underlines the size and depth advantages compared to packages. Source: P2F Semi
In an attempt to take advantage of the greater size and depth achievable by layered PCBs as compared to packages, some design teams have tried implementing separate analog and digital ground planes to avoid current-based EMI issues between the two types of circuits. Unfortunately, this proved to have the annoying tendency of creating a dipole antenna on the board. Connecting separate ground planes with traces in order to ameliorate such a problem often leads to generating another antenna.
Frequency and bandwidth are not the only sources of EMI, however, and judging the EMI potential of a chip or circuit by such terms is not always sufficient to assess the risk of their being a source of noise. High precision ADCs, for instance, are more accurately evaluated for EMI not by their Fmax, but by their sampling rate.
A long-standing practice of board designers is to separate analog and digital components on a board and allow only DACs or ADCs to straddle the boundary between them. In addition, digital and analog signal traces are segregated to their own regions—passing one thru another’s domain is studiously avoided. Finally, it is considered imperative to not cross an analog or digital trace over the other.
There are times, however, when the necessity of passing one kind of signal trace thru the other’s domain or crossing analog and digital signal traces cannot be evaded. In such circumstances, experienced PCB designers make sure that the design rule violation occurs above a ground plane reference. Not doing so is an invitation to precipitating crosstalk thru induction.
Nevertheless, clean partitions between analog and digital signaling domains on PCBs are almost impossible at this point. The SoC devices contain both analog/RF and digital circuits in quantity and can only rarely be placed on the board astride domain boundaries as ADCs and DACs are. Even chips that appear entirely digital in function can have a small but important embedded analog component—such as a DSP with an internal PLL.
As a rule, PCB designers ground mixed-signal devices to the same grounding plane as they do for purely analog components. However, for chips with a relatively small analog component, it can get trickier. Often enough, chip vendors will provide separate analog and digital ground pins and instruct board engineers to bring both pins to the digital ground reference plane. Be prepared, though, to place a decoupling cap with the analog ground pin. If, on the other hand, a device vendor instructs board engineers to tie the analog and ground pins together, that trace should then be brought by the shortest distance possible to analog ground.
A tremendous advantage PCBs have over chips and packages is the ability to deploy large, thick copper ground planes. Such a plane provides a consistent impedance across a wide range of frequencies, reduces R and L components, and helps with thermal conductivity.
To prevent large transient currents from travelling across such a ground plane from high frequency digital switching activity and causing EMI problems for analog devices connected to the same reference plane, board designers are often forced to cut the plane into a digital and an analog portion. These separate planes can be connected using Schottky diodes or similar high-impedance methods to prevent transient voltage building up between planes while simultaneously blocking current spikes from crossing between them.
It should be noted that the above rules and solutions are not scripture. Situations vary, so flexibility and adaptability are required. The EDA and PCB companies can provide additional expertise, and there are continual efforts to develop improved dielectric materials for board layers that are superior insulators while still being cost effective and manufacturable.
Holistic SoC design
So far, in this series, we have discussed chip, package and PCB issues as separate entities. To treat them serially and individually during SoC design, however, would be a woeful error, as it inevitably leads to iterative design cycles with significant rework, ruined schedules, and jarring cost overruns. What is needed is a more holistic approach that integrates design needs across multiple levels, a topic which we will examine in the next installment.
Kedar Patankar, chief technology officer (CTO) at P2F Semi, is a semiconductor industry veteran with 23 years of experience in design, development, and customer relations.
Other articles in this series
- SoC PDN challenges and solutions
- SoC offers design alternative, and challenges, compared to SiP
- PCB Design Considerations and Tools
- Synopsys Tackles SoC Design with Unified Circuit Simulation Flow
- Heterogeneous Integration and the Evolution of IC Packaging