Stable regulation of output voltage is an operational imperative of linear regulators. While this topic has been discussed in the past (**Reference 1** and **Reference 2** ), this article provides a practical, straightforward look at linear regulator regulation, stability, and compensation, including equations and illustrations, useful to design engineers of many different experience and education levels.

The five main types of linear regulators are the standard NPN, NPN pass transistor, PNP pass transistor, P-channel FET, and N-channel FET regulators. All linear regulators consist of three key elements:

- A pass element
- A band gap voltage reference
- An error amplifier

The output-voltage regulation of the linear regulator is achieved by feedback. **Figure 1a** illustrates the feedback concept using the PNP pass transistor regulator (Figure 1a, without the coupling transformer).

The resistor divider, error amplifier, and pass element of the PNP pass transistor regulator form a closed loop. The output voltage, V_{OUT} , provides a feedback voltage through the resistor divider, V_{C} = V_{OUT} * R_{2} / (R_{1} + R_{2} ), to the non-inverting input of the error amplifier. The band gap reference output (V_{REF} ) is a high-precision, fixed voltage that is tied to the inverting input of the error amplifier.

The error amplifier, essentially an op amp, then makes V_{C} equal to V_{REF} by sourcing a ground current to the base of the PNP transistor. The PNP transistor, in turn, supplies sufficient output current to keep V_{OUT} at a certain value. A fraction of this value, V_{C} , is equal to V_{REF} . The regulated output voltage, therefore, is defined as (**Equation 1** ):

_{OUT}= V

_{REF}x (1 + R

_{1}/R

_{2})

This equation illustrates that the feedback is negative, and the adjustment of the output voltage resulting from the feedback is in opposite polarity to the “original” change to the output voltage. In real-life applications, sufficient negative feedback is required for closed loop stability.

For example, imagine that a small disturbance is introduced to the loop. The coupling of a small sinusoidal signal to the PNP pass transistor regulator through a transformer models this disturbance (**Figure 1a** ).

__Click to Enlarge Image__Figure 1a: Closed Loop Phase Shift Model

Initially, the small signal has a value of ΔV_{A} at point A, and a value of ΔV_{B} at point B. The signal at point B then travels through the loop and eventually arrives at point A, with a value of ΔVB’. Although ΔV_{A} and ΔV_{B} ’ have the same magnitude (unity gain), there is a difference in phase (in degrees) between the two.

To simplify this analysis, assume that the error amplifier introduces a “perfect” negative feedback to the loop. That is, if there were only the error amplifier in the feedback loop, ΔV_{A} would lag ΔV_{B} ’ by -180 degrees (**Figure 1b** ).

__Click to Enlarge Image__Figure 1b: Closed Loop Stability Map

However, because of the pass element’s built-in capacitance, it introduces a phase shift that reduces the perfect -180deg phase difference by a value between 0deg and -180deg (counter-clockwise, with -180deg as the starting point).

This brings us to the *Bode plot* , a simple yet effective tool that is widely used to analyze closed-loop stability. A Bode plot includes loop-gain and phase-shift curves. These curves track the movements of poles and zeros created by the impedances of the components that form the loop. The behaviors of the poles and zeros determine loop stability.

A pole decreases the loop gain slope by -20dB/decade at its pole frequency, f_{p} . It also introduces a -90° phase shift (counter clockwise) from the frequency one decade below f_{p} (f_{p} /10) to the frequency one decade above f_{p} (10f_{p} ), with a -45deg phase shift at f_{p} . Both loop gain slopes decrease and phase shifts are additive, meaning that each additional pole decreases the loop gain slope by another -20dB/decade, and increases the phase shift by an additional -90deg. An RC pair in low-pass filter configuration models a pole, with its f_{p} defined as (**Equation 2** ):

_{p}= 1/2πRC, expressed in Hz

A zero, on the other hand, increases the loop gain slope by +20dB/decade at its zero frequency (f_{z} ). It also introduces a +90deg phase shift (clockwise) from the frequency one decade below f_{z} (f_{z} /10) to the frequency one decade above f_{z} (10f_{z} ), with a +45deg phase shift at f_{z} . Loop gain slope increase and phase shift created by a zero are also additive. An RC pair in high-pass filter configuration with its f_{z} shown by the following equation models a zero (**Equation 3** ):

_{z}= 1/2πRC, expressed in Hz

In Figure 1a, the loop gain (A) of the closed loop is given as (**Equation 4a** ):

_{A}/ΔV

_{B}|), expressed in dB

The single most important stability indicator of a closed loop is phase margin, defined as the difference (in degrees) between -180deg and the total phase shift of the loop at the frequency where the loop gain is 0dB (unity gain – when ΔVA and ΔVB’ have the same magnitude). Phase margin is a positive number (clockwise) between 0deg and 180deg, and is expressed as (**Equation 4b** ):

*where phase shift is a negative number (counter clockwise) between 0deg and -180deg.

To keep the loop stable, the phase margin must be no less than 45deg (Figure 1b). If a 45deg phase margin cannot be achieved by the intrinsic architecture of the linear regulator, some form of compensation, either internal or external, is required.

To analyze the loop stability of linear regulators, we will start with the standard NPN regulator as an example. There are two poles in the standard NPN regulator: a dominant pole (P_{INT} ), created by the intrinsic capacitance of the regulator, and a power pole (P_{PWR} ), created by the pass element. P_{INT} and P_{PWR} occur at the following frequencies (**Equation 5a** ):

_{INT}) = 1/2πR

_{INT}C

_{INT}

*where R

_{INT}and C

_{INT}are the regulator’s intrinsic resistance and capacitance (

**Equation 5b**)

_{PWR}) = 1/2πR

_{PWR}C

_{PWR}

*where R

_{PWR}and C

_{PWR}are the pass element’s resistance and capacitance

The NPN Darlington pair is in a common collector configuration, so its output impedance is very low (i.e., R_{PWR} C_{PWR} is very low). Therefore, P_{PWR} occurs at a very high frequency (Equation 5b), whereas P_{INT} occurs at a lower frequency because of the regulator’s relatively high capacitance (Equation 5a).

Still, P_{PWR} can occur at a frequency below the 0dB crossover point, which may create a less-than-45deg phase margin. In this case, the loop becomes unstable, which creates a need for compensation (**Figure 2** ).

__Click to Enlarge Image__Figure 2: Standard NPN Regulator Bode Plot

(Uncompensated and Dominant Pole Compensation)

The standard NPN regulator employs an internal compensation scheme known as *dominant pole compensation* , achieved by adding intrinsic capacitance to the regulator. This additional capacitance moves P_{INT} to an even lower frequency (Equation 5a) with no effect to P_{PWR} , enabling it to occur at a frequency above the 0dB crossover point. The phase margin is now greater than 45deg, resulting in a stable loop. As such, the standard NPN regulator is stable without external compensation (Figure 2).

The NPN pass transistor regulator also has a dominant pole (P_{INT} ) and a power pole (P_{PWR} ). Like the standard NPN regulator, the NPN pass transistor is in a common-collector configuration with low output impedance. However, the NPN transistor is driven by a PNP transistor with high impedance. The net effect is that its output impedance, although high in comparison to other types of linear regulators, is not as high as that of the standard NPN regulator. Therefore, P_{PWR} occurs at a frequency lower than of the standard NPN regulator, and usually below the 0dB crossover point. The result is a less than 45deg phase margin, where compensation is needed for loop stability (**Figure 3** ).

__Click to Enlarge Image__Figure 3: NPN Pass Transistor Regulator and N-channel FET Regulator Bode Plot

(Uncompensated and Output Cap Compensation, ESR Not Critical)

Because of the relatively low frequency of P_{PWR} , the NPN pass transistor regulator cannot be stabilized by dominant-pole compensation alone. Instead, a zero must be placed between P_{INT} and P_{PWR} to increase the phase margin to at least 45deg (Figure 3). This is accomplished by using an external compensation method, such the addition of an output capacitor next to V_{OUT} . The frequency of the added zero (Z_{COMP} ) is defined by (**Equation 6** ):

_{COMP}) = 1/(2π x ESR x COUT)

where ESR is Equivalent Series Resistance of the output capacitor.

Because P_{PWR} of the NPN pass-transistor regulator still occurs at a higher frequency, output-capacitor selection is fairly easy. As long as f(Z_{COMP} ) is lower than f(P_{PWR} ), C_{OUT} can be small, and ESR is not critical.

The PNP pass-transistor regulator, on the other hand, requires more careful selection of an output capacitor. Its pass element, the PNP transistor, is in a common emitter configuration, which exhibits high output impedance. This is important on two fronts:

- P
_{PWR}occurs at a frequency lower than in the NPN pass transistor regulator. - The impedance of the load, created by load resistance and output capacitance, becomes a significant contributor to loop stability by adding another low-frequency load pole (P
_{L}) to the Bode plot. The frequency of P_{L}is expressed as (**Equation 7**):f(P _{L}) = 1/(2π R_{LOAD}C_{OUT})

Typically, R_{LOAD} and C_{OUT} are higher than the regulator’s intrinsic resistance (R_{INT} ) and capacitance (C_{INT} ), which makes P_{L} occur at a frequency lower than f(P_{INT} ). It is immediately obvious that the PNP pass-transistor regulator is not stable, even with dominant pole compensation (**Figure 4a** ).

__Click to Enlarge Image__Figure 4a: PNP Pass Transistor Regulator and P-channel FET Regulator Bode Plot

(Uncompensated and Output Cap Compensation with Correct ESR Value)

A zero must be added to compensate for this instability. Again, this is accomplished by the addition of an output capacitor next to V_{OUT} .

In this case, the placement location of the zero in the frequency space is critical, because it translates to a careful matching of the output capacitor’s capacitance and ESR.

The zero must occur somewhere between P_{INT} and P_{PWR} (Figure 4a). Because P_{PWR} occurs at a relatively low frequency, the “space” between P_{INT} and P_{PWR} is narrow; hence, the choice of f(Z_{COMP} ) is narrow and is demonstrated as (**Equation 8** ):

_{INT}) < f(Z

_{COMP}) < f(P

_{PWR})/10

This equation shows that Z_{COMP} must occur above f(P_{INT} ), and at least one decade below f(P_{PWR} ). This is because Z_{COMP} needs the full one decade above f(Z_{COMP} ) to fully realize its +90deg phase shift. As Equations 5a, 5b, 6, and 8 show, for loop stability at any given capacitance value, the ESR must satisfy the following (**Equation 9** ):

_{INT}C

_{INT}> ESR > 10R

_{PWR}C

_{PWR}/C

_{OUT}

If the ESR is either too high or too low, it is out of range.

The ESR is too high when the following condition exists (**Equation 10** ):

_{INT}C

_{INT}/C

_{OUT}

In this condition, Z_{COMP} occurs at a frequency below f(P_{INT} ) (**Figure 4b** ).

__Click to Enlarge Image__Figure 4b: PNP Pass Transistor Regulator and P-channel FET Regulator Bode Plot

(Uncompensated and Output Cap Compensation with High ESR Value)

Additionally because of the narrow space between P_{L } and P_{INT} , Z_{COMP} can be within one decade of f(P_{INT} ). This prevents Z_{COMP} from realizing its full +90deg phase shift. As a result, the phase margin may not rise above 45deg and, hence, the loop is unstable.

On the other hand, ESR is too low when the following is true (**Equation 11** ):

_{PWR}C

_{PWR}/C

_{OUT}

Here, Z_{COMP} occurs within one decade below f(P_{PWR} ), which prevents it from realizing its full +90deg phase shift (**Figure 4c** ).

__Click to Enlarge Image__Figure 4c: PNP Pass Transistor Regulator and P-channel FET Regulator Bode Plot

(Uncompensated and Output Cap Compensation with Low ESR Value)

Therefore, the phase margin will not rise above 45deg, and the loop, again, is unstable.

The P-channel FET regulator has its pass element (the P-channel FET) in a common source configuration, similar to a PNP transistor in a common emitter configuration with relatively high output impedance. As such, the P-channel FET regulator has loop stability behavior similar to that of the PNP pass transistor regulator. The P-channel FET regulator, therefore, requires a carefully selected output capacitor to keep the loop stable (Figures 4a, 4b, and 4c).

Finally, the N-channel FET regulator has its pass element (the N-channel FET) in a common-drain configuration similar to an NPN transistor in a common-collector configuration. In reality, the N-channel FET regulator’s output impedance is not as low as that of the standard NPN regulator. Rather, it is comparable to that of the NPN pass-transistor regulator. There, the N-channel FET regulator exhibits similar loop stability behavior to the NPN pass-transistor regulator, which requires an output capacitor for compensation. However, in this case, the ESR of the output capacitor is not as critical (Figure 3).

In conclusion, the Bode plot is an effective tool for analyzing closed loop stability of linear regulators. Phase margin is the most important indicator of stability. If a greater-than-45deg phase margin cannot be achieved by the intrinsic architecture of the linear regulator, an internal or external compensation method, such as an output capacitor, can ensure closed loop stability. **Table 1** summarizes the loop stability characteristics and compensation methods for each of type of linear regulator.

__Click to Enlarge Image__Table1: Summary of loop stability characteristics and compensation methods

**References:**

1. “*Linear Regulators: Theory of Operation and Compensation* ,” Simpson, Chester, May 2000, National Semiconductor Application Note 1148

2. “*The Art of Electronics* ,” Horowitz, Paul and Hill, Winfield, Cambridge University Press, 2nd Edition (July 1989), Chapter 2 (Section 2.04), Chapter 3 (Section 3.08), Chapter 4 (sections 4.33, 4.34, 4.35)

**About the Author**

* Qi Deng * is a Senior Product Marketing Engineer for Analog and Interface Product Division at Microchip Technology, Inc, www.microchip.com . Qi has over ten years of experience in the semiconductor and electronics industry, including time spent in engineering and management positions with Delphi Delco Electronics, General Electric Appliances, and National Semiconductor. He earned his Bachelor of Science in Physics degree from Peking University, his Masters of Science in Electrical Engineering (MSEE) degree from Purdue University, and his Master of Business Administration (MBA) degree from the University of Michigan. Qi is responsible for strategic marketing and product management for Microchip’s analog power management products.

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