Analog circuitry is essential for all real world systems. Sensors, for example, which are a primary driver for the growing IoT market, require analog for measurements (e.g., temperature, pressure, light levels, etc.) and for converters to convert to the digital world (A/D and D/A). However, although digital design productivity has improved massively since the introduction of synthesis, advanced place and route and timing-driven design, analog design still relies on circuit simulation, manual layout and verification.
The bottleneck in the manual flow is that typically a circuit designer designs and simulates a block, then passes on the schematic to a layout engineer, who will take constraints from the circuit designer (often in notes in the schematic, e.g., “these devices need to be matched”) and perform a layout. It may take hours or even days to lay out the design, then hand back the parasitic information to the circuit designer to check the performance. If performance is not met, the loop continues – hence the bottleneck. Also, the designer might want an initial estimate of the block size in order to produce a floorplan of the top level, which again requires a layout to be generated, maybe using a prototype layout in order to speed things up a little.
There have been several incremental improvements to the flow over the years – for example, the use of parameterized cells to automate device generation. However, automatic placement and routing of analog designs has been largely unsuccessful. Techniques such as placing based on the schematic require manual movement of devices, and, without routing knowledge, cannot give any accurate area estimation. Other placement techniques can achieve better results, but typically generate just one layout, which may or may not be routable, so again manual modification is required (which more often than not can be extensive).
Constraint-driven placement is certainly an improvement, but the constraints need to be automatically generated as much as possible or else the circuit designer will spend much time in setting them up and scripting the placement. Additionally, Constraint-driven placement should generate multiple different topologies so that circuit designers can find the best topology for their application. Typical constraints include net widths, spacing and shielding; common centroid layout of devices, alignment or relative positioning and clustering of devices; guard rings and block height/width constraints. The ability to change constraints simply and to then re-generate a full layout allows user control of the layout process but with much faster runtime than a full manual layout.
The placement must include simultaneous consideration of routing, otherwise the design may not be able to be routed by a separate router. Thus simultaneous generation of many fully placed and routed designs will allow the circuit designer to extract parasitics quickly before handing off the design to the layout engineer for final tweaking and verification.
In summary, there is no “one size fits all” solution for analog layout, but an automated constraint-driven system that requires no user scripting is possible (and available) and can make designers much more productive.