Converters get their Powerpoint day at ISSCC

Analog-to-digital converters garnered significant attention at ISSCC this week, with a 16-paper session devoted to oversampling (sigma-delta) devices and an eight-paper session on Nyquist-rate devices, out of 255 full-length papers; they also figured prominently in the design tutorials, evening sessions, and circuit-design forums. All the converter presentations involved real, not just simulated or hypothetical, devices and nearly all were fabricated in standard 180-nm CMOS process technology.

Emphasis was on reducing power, increasing speed, and boosting dynamic range, generally in the 10 to 14-bit arena. Converters combined innovative architectures with meticulous attention to every source of static and dynamic error, noise, delay, glitch, instability, and power drain, and then compensated for, canceled, or minimized every one of these, while not incurring collateral performance penalties. Several converters provided sub-1V and milliwatt-range operation.

Among the oversampling devices, the clear trend was to push speeds and bandwidths high enough that the converters could operate in IF and even low-band RF regimes. Analog Devices, for example, presented a 375 mW bandpass ADC for multistandard TV receivers, which is clocked at 264 MHz and includes 12-dB of AGC, and achieves 90 dB dynmiac range with a bandwidth of 8.5 MHz centered on a 44-MHz frequency. Even old-and-new radio got attention, with highly integrated modulator for AM/FM/IBOC which eliminates an external VGA and AM channel filter, while yielding 118 dB dynamic rnage in AM mode and 98 dB in the FM mode, and 90 dB SFDR for IBOC reception. The 210 mW, 1.8V device was developed by a team at Delft University of Technology and Philips (Netherlands).

No need to stop as you approach one-volt supply marker, either, despite the noise and headroom challenges of reduced supply rails. From Universidade Nova de Lisboa and Acacia Semiconductor, both of Portugal, came a sigma-delta modulator operating from 0.9V while dissipating just .2 mW, with a 10 kHz bandwidth, with a resultant 80 dB SNDR (signal-to-noise-and-distortion ratio) and 83 dB dynamic range. If that supply is not low enough, a modulator from the Chinese University of Hong Kong and Columbia University pushed down to a 0.5V supply, accepting 1V input signals and delivering 74 dB SNDR at a 25 kHz bandwidth with 370 microwatts dissipation.

For Nyquist converters, it's mostly about power efficiency, defined by the figure of merit of picojoules (pJ) per conversion step. The 1 pJ/step barrier is gone, with converters pushing down to and below 0.5 pJ/step. To do this, they are using offset cancellation, digital offset calibration, and redundancy, as well as “reusing” current in internal op amps.

A team from University of California (San Diego) and Conexant showed a 10 bit, 50 Msps ADC which used the same op amp in two stages as residue amplifiers, which avoids settling and delay problems incurred by turning an op amp on and off; to do this, they had to overcome offset and 1/f noise problems that sharing brings. Final performance from a 1.8V supply at 18 mW, with a 1 MHz and a 20 MHz input, is ENOB and SNDR of 9.2/8.8 bits and 56.9/54.6 dB, respectively.

For sensing and monitoring applications where power consumption trumps sampling speed, an MIT team has pushed ultra-low-power SAR (successive approximation register) architectures from their traditional 8-bit world to 12 bits, achieving 200 ksps conversions at lower resolution and 100 ksps at the higher resolution. Each source of dissipation needed attention: for example, since the efficiency of SAR-based designs degrades compared to sigma-delta designs as resolution is boosted, the team used offset-compensating regenerative latches, which have a superior power0-delay product compared to the more common linear stages. Even at the higher resolution, power consumption when operating from a 1V supply is just 25 microwatts.

Beyond device-specific papers, special sessions examined broader topics. A discussion session “CMOS RF Design at 90 nm and Beyond” looked at prospects for clash and cooperation as analog circuits meet the next process node, and vendors strive to develop high-performance mixed-signal SOCs. If you thought today's process and device models were complicated and risky, get set for even more of these factors, noted presenters Sally Liu of TSMC and Behzad Razavi of UCLA, who presented basic facts and dilemmas of RF modeling and design challenges, respectively, for deep-submicron CMOS. When it comes to putting high-speed digital circuits in close proximity to sensitive, wideband RF functions, an old saying unfortunately applies to their signals: “what's mine is mine, and what's yours is mine, too.”

You can access the 111-page advance program at

1 comment on “Converters get their Powerpoint day at ISSCC

  1. Miriam
    October 21, 2021

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