Faster, smaller, and less expensive are the guiding words of new electronics and it's certainly true for digital-to-analog (D/A) converters. Manufacturers of these omnipresent components are always trying to squeeze a little more from their designs, and they are aided by architecture and process type to get to the next level. However, there are challenges even if the fabrication process provides smaller size and metal pitch to increase the speed. As with anything analog, there are always tradeoffs. For example, reducing supply voltage makes improving the accuracy a significant challenge.
Let's take a moment to step back and look at some of the important points about digital-to-analog converters. For example, there D/A converter specifications that must be considered when considering which converter is appropriate and they include resolution, accuracy, quantizing error, full-scale error, gain error, offset error, differential non linearity (DNL), integral non linearity (INL).
Resolution describes the smallest standard incremental change in output voltage of a D/A converter or the amount of input voltage change required to increment the output of an A/D converter between one code change and the next adjacent code change. A converter with n switches can resolve 1 part in 2n. The least significant increment is then 2'n, or one least significant bit (LSB). In contrast, the most significant bit (MSB) carries a weight of 2:1. Resolution applies to D/A converters and A/D converters, and may be expressed in percent of full scale or in binary bits. For example, a 12-bit DAC would exhibit an output voltage change of 0.0244% of full scale when the binary input code is incremented one binary bit (1 LSB). Resolution is a design parameter rather than a performance specification; it says nothing about accuracy or linearity.
Accuracy is sometimes considered to be a non-specific term when applied to D/A or A/D converters. A linearity spec is generally considered as more descriptive. An accuracy specification describes the worst case deviation of the D/A converter output voltage from a straight line drawn between zero and full scale; it includes all errors. A 12-bit D/A converter could not have a conversion accuracy better than ±12 LSB or ±1 part in 212+1 (±0.0122% of full scale) due to finite resolution. Actually, ±0.0122% FS represents a deviation from 100% accuracy; therefore accuracy should be specified as 99.9878%. However, convention would dictate 0.0122% as being an accuracy spec rather than an inaccuracy (tolerance or error) spec. Accuracy as applied to an A/D converter would describe the difference between the actual input voltage and the full-scale weighted equivalent of the binary output code; included are quantizing and all other errors. If a 12-bit A/D converter is stated to be ±1 LSB accurate, this is equivalent to ±0.0245% or twice the minimum possible quantizing error of 0.0122%. An accuracy spec describes the maximum sum of all errors including quantizing error, but is rarely provided on data sheets as the several errors are listed separately.
Scale Error (full scale error) is the departure from design output voltage of a D/A converter for a given input code, usually full-scale code. Scale errors can be caused by errors in reference voltage, ladder resistor values, or amplifier gain. Scale errors may be corrected by adjusting output amplifier gain or reference voltage.
Gain Error in a D/A converter with current and voltage mode outputs, the current output could be to scale while the voltage output could exhibit a gain error. The amplifier feedback resistors would be trimmed to correct the gain error.
Offset Error (zero error) is the output voltage of a DAC with zero code input. Offset error is usually caused by amplifier or comparator input offset voltage or current; it can usually be trimmed to zero with an offset zero adjust potentiometer external to the D/A converter or A/D converter. Offset error may be expressed in percent fulscale or in fractional LSB.
Differential Non-Linearity indicates the difference between actual analog voltage change and the ideal (1 LSB) voltage change at any code change of a DAC. For example, a DAC with a 1.5 LSB step at a code change would be said to exhibit 12 LSB differential non-linearity. Differential non-linearity may be expressed in fractional bits or in percent fullscale. Differential linearity specs are just as important as linearity specs because the apparent quality of a converter curve can be significantly affected by differential non-linearity even though the linearity spec is good.
Integral nonlinearity error is the deviation of the values on the actual transfer function from a straight line. This straight line can be either a best straight line which is drawn so as to minimize these deviations or it can be a line drawn between the end points of the transfer function once the gain and offset errors have been nullified. The second method is called end-point linearity and is the usual definition adopted since it can be verified more directly. The name integral nonlinearity derives from the fact that the summation of the differential nonlinearities from the bottom up to a particular step, determines the value of the integral nonlinearity at that step.
Example of Integral non linearity compared to temperature
The MAX5732, MAX5733, MAX5734, and MAX5735 deliver a maximum integral non-linearity of 0.024 percent FSR and a differential non-linearity of less than 1 LSB. They each offer four output voltage ranges: 0 to +5 V, 0 to +10 V, -2.5 to +7.5 V, and ±5 V. They also offer a three-wire serial interface for linking up with microprocessors and DSPs.
Example of Integral non linearity versus input code
Settling Time is the elapsed time after a code transition for D/A converter output to reach final value within specified limits, usually ±12 LSB. Settling time is often listed along with a slew rate specification; if so, it may not include slew time. If no slew rate spec is included, the settling time spec must be expected to include slew time. Settling time is usually summed with slew time to obtain total elapsed time for the output to settle to final value. Slew Rate is an inherent limitation of the output amplifier in a D/A converter which limits the rate of change of output voltage after code transitions. Slew rate is usually anywhere from 0.2 to several hundred volts/μs. Delay in reaching final value of D/A converter output voltage is the sum of slew time and settling time.
Manufacturers of D/A converters are always dealing with tradeoffs when trying to meet customer design requirements. One of the key challenges for D/A converters,” said James Caffrey, Product Marketing Manager for Precision Converters at Analog Devices (ADI), “is providing increasing levels of performance while simultaneously meeting the demands of reducing package size and power consumption. Meeting these conflicting demands often needs breakthroughs in more than one aspect of the product design,” he said. For example, ADI recently introduced the AD5641, a member of Analog Devices' nanoDAC family, which combines both packaging and architecture innovation to simultaneously increase the performance and reduce the package size compared to existing products. The company says the AD5641 is the world's smallest D/A converter and provides 14-bit resolution in an SC70 package.
Analog Devices AD5641 Block diagram
Texas Instruments also offers several products that help deal with the tradeoffs and meet the different needs of customers. The DAC2932 fills a niche between the slower, precision R-2R D/A converters that operate around 1MHz or less, and the >500 MHz D/A converters such as the DAC5686 that offer features such as interpolation and numerically controlled oscillators, but at the cost of increased power dissipation. The DAC2932 is a dual 12-bit, current-steering D/A converter. It has 2 mA output, operates up to 40MHz, consumes only 25mW, and offers four 12-bit control D/A converters on board allowing the user to calibrate systems errors such as gain and offset.
“As with any product, reducing time-to-market is an important aspect,” observed Paul Maddox, Fujitsu digital-to-analog group. “Achieving this for a system-critical component such as a D/A converter can have a direct benefit to the customers' system time-to-market. The challenge comes from bringing the advances in dynamic performance for the data converter to market faster with all the risk associated with such full custom analog developments.” Fujitsu Microelectronics tackles this challenge by using its multi-project wafer flow to verify advance developments and decouple this from the final product. This approach gives a far greater assurance of the schedule to reach production approval and enables early access to reliable performance data. This was demonstrated during the course of the launch of the MB86064 dual 14-bit 1GSPS D/A converter, first announced at the end of January 2003 and approved for production by the end of the year.
In most areas such as video and wireless modems, higher levels of integration are required. For markets that are characterized by high volumes, Intersil increases the channel count per device and the amount of digital integration for increased functionality. The company says it will continue to address markets that it can use both standard products and ASSPs. “There is also a need for engineers to be able to quickly evaluate the performance of a D/A converters, to maximize time-to-market requirements,” said Steve Smith, Product Marketing for Intersil. Additionally, Intersil has a service called Test Drive that provides an easy method for engineers to get quick evaluations over the web by logging on its Test Drive home page. Through this service, customers can specify what performance parameter they would like the company to measure for them, typically with 3-day turnaround times.
The TDA8777 from Philips Semiconductor consists of three separate 10-bit video Digital-to-Analog Converters (DACs) with complementary outputs. They convert the digital input signals into analog current outputs at a maximum conversion rate of 330 MHz. The D/A converters are based on current source architecture. A sync pulse can be added to the green signal (Sync-On-Green) to allow devices driven by the video DAC to be synchronized.
The TDA8777 has a Power-down mode to reduce power consumption during inactive periods. The TDA8777 is fabricated in a CMOS process that ensures high functionality with low power dissipation.
“Regardless of the application area, if designers are to take advantage of new D/A converter announcements then confidence in the product's performance is vital,” said Fujitsu's Mr. Maddox. This can only be met by quoting meaningful minimum guaranteed specifications, in particular dynamic parameters such as spurious free dynamic range (SFDR), and adjacent channel leakage ratio (ACLR). To be meaningful a specification needs to quoted under anticipated operating conditions. For example, quoting single carrier UMTS ACLR performance at 62MHz but then inferring that the product can support 4 UMTS carriers at, say, 122 or 140MHz is not very reassuring,” he added.
Fujitsu says completion of characterization prior to production approval has led to an improvement in quoted ACLR performance. The figure when generating 4 UMTS carriers at 276MHz has increased to 74dBc, using a D/A conversion rate of 737MSPS.
“As manufacturers strive to develop smaller products with longer battery life and with lower power and heat dissipation, especially in the mobile communications field, increased performance often needs to be traded off against reduced power consumption and board area,” said ADI's Mr. Caffrey. “Consequently there has been a continual push for cost-effective components that deliver increased performance in smaller packages, similar to products like the ADI nanoDAC. This family addresses these challenges by consuming considerably less power and smaller space than comparable solutions, while simultaneously increasing performance.
Linear Technology introduces the LTC2602 dual and LTC2604 quad 16-Bit VOUT D/A converters. Also available in 12-Bit and 14-Bit versions, these converters guarantee monotonic performance over temperature with DNL of ±1LSBmax , which is critical in control loop applications. The LTC2604 consume only 250 μA per D/A converter and drop to 0.25 μA per D/A converter in power-down mode.
What the future holds
“As speed and resolutions increase,” says Intersil's Steve Smith, “the demand for easier to use interfaces such as LVDS will grow in popularity. Trade-offs will have to be analyzed in each specific market in relationship to the power consumed with these interfaces,” he said.
D/A converters provide conversion from the digital to the analog domain and as such are the bridge between the digital processing and the system's analog response. According to TI the performance of the D/A converter often directly determines the quality of the end customer experience. Improving D/A converter performance while continuing to drive down the power and cost of the conversion will facilitate new applications and allow customers deliver improved value to their end customers.
Analog Devices, Inc.
Tel: 800-ANALOGD (262-5643)
Tel: (321) 724-7000
Linear Technology Corp.
Maxim Integrated Products, Inc.
Tel: 408-737-7600 or 800-998-8800
National Semiconductor Corp.
Tel: +1 408 474 5065 or,
Tel: +31 4027 66743
Texas Instruments Inc.
Tel: 800-477-8924, ext. 4500
Tel: +44 (0) 131 272 7000