In DAC BASICS, Part 4: The Pesky DAC Output Glitch-Impulse, we talked about the dynamic specification of glitch and its impact the digital-to-analog converter (DAC) linearity. This characteristic is inconsistent across various R-2R and string DAC topologies, providing options as you work through the DAC selection process. In contrast, the DAC’s settling time characteristics are consistent across both topologies (Figure 1 ). These specifications provide information about your DAC’s bandwidth. These DAC characteristics are dependent on the digital code input changes and output amplifier.
Figure 1 may look familiar, if you understand a stand-alone buffer amplifier’s response to full-scale input step response. DAC settling time characteristic descriptions are consistent with the operational amplifier’s (op amp) performance.
Figure 1 shows a DAC’s amplifier output with a full-scale digital step input.(1) This type of output response is initiated by applying a step-response signal to the stand-alone buffer amplifier’s input, or changing the DAC code from negative to positive full-scale. In terms of Figure 1 , we have two definitions of a DAC’s settling time. The first type is settling time, input-to-output, which spans the dead, slew, recovery, and linear-settling regions (see label at bottom of Figure 1 ). The second is similar to the first, but minus the dead time (left).
DAC dead time occurs at the moment the code is loaded into the DAC to the time when the analog output starts to slew towards its final analog value. Dead time details consist of the time it takes for the DAC to load the input digital code, internal DAC switching times, and output amplifier’s propagation delay. In many applications such as video, this dead time can be ignored.
Following dead time is slew time. During slew time, the DAC output transitions from 10 to 90 percent of the final value. This slew condition is initiated as the DAC’s internal amplifier inputs exceed ∼ 100 mV to 1 V(2) , depending on the individual DAC op amp.
While the amplifier is in this slew condition, it cannot respond to incremental input DAC digital code changes. Basically, the amplifier’s input stage is overdriven and the amplifier output change rate is at its maximum. Generally, this is controlled by the amplifier’s characteristics found following the DAC, whether internal or external.
Recovery time, also known as the large signal-settling time, happens while the DAC’s output stage overshoots the final value. The overshoot goes beyond the DAC’s output stage linear region and is not characteristic of the linear-settling activity. It may be possible to avoid this level of overshoot by slightly reducing the DAC’s output range.
As the output voltage nears its final value the voltage across op amp inputs reenter their linear range. As a result, the rate of change reduces to make a smooth landing to the final value.
Finally, the DAC enters its linear-settling or small-signal settling area as it approaches a final output value. Once the DAC settles within a pre-determined error-band, the linear-settling time concludes.
Settling time versus DAC bandwidth
The specified maximum settling time for any DAC should be in the datasheet’s electrical characteristics table. You can convert this specification to bandwidth by doubling it, then taking its inverse. For instance, a DAC settling time of 5 μ s has a bandwidth of 1 / (2 x settling time), or 100 kHz. More importantly, the actual time that the DAC requires to settle is key in many applications.
Settling time is critical in arbitrary waveform generator applications or video displays where the full-scale change from white to black is under 16 ns for a 1024×768, 60-Hz screen.
Figure 2 shows an example of the DAC’s settling time using the DAC9881, an 18-bit, single-channel, low-noise, voltage output digital-to-analog converter.
In this case, a large signal transition is well-behaved so that recovery time is shorter than the linear settling time. This linear settling time follows the characteristics of a single-pole function.
As you toggle DACs across their output analog range, make sure that you understand the conditions of the settling time specification. For example, using the DAC9881’s datasheet, settling time is specified as 5 μ s when stepping from code 0x04000 to 0x3C000 (almost a full-scale step). Additionally, the settling time window is +/- 0.003%, which is approximately eight times larger than one least significant bit (LSB) (0.0004%) of the 18-bit DAC.
Not all users are interested in stepping the DAC from zero scale to full scale. Many times the user’s application calls for smaller code steps versus full scale.
Users program the DAC to step up or down a few mV, or maybe a volt. In this environment, the DAC may never enter into a slew rate condition (Figure 2 ).
Figure 3 shows an example where the DAC is stepping up 1/32 or 150 mV of a full-scale step.
Notice that the overshoot and recovery period is much smaller than previously shown.
A DAC’s precise settling time may or may not be of interest. This specification becomes particularly important in high-speed applications, such as video displays. Figure 1 shows the fundamental definitions of the regions in a full-scale settling time event. These portions as defined in this figure map quite closely to an op amp.
From another perspective, the smaller signal settling characteristics can be interesting. A slight reduction in range compared to full-scale can be very productive.