Current Feedback Amplifiers (CFA) provide the highest Large Signal BandWidth (LSBW), but relatively poor DC precision. The elements creating that poor DC precision will be detailed here. Of particular interest is the CMRR error in the CFA design. That low CMRR arises from the input buffer gain being <1.0. The more recent Fully Differential Amplifiers (FDA) offer both CFA and VFA versions. The CFA based versions will also have poor DC accuracy while more recent “precision” VFA based FDAs can provide much improved DC accuracy. Those VFA-based FDAs do come with some added DC error sources beyond the typical op amp terms that will be described here.

DC accuracy for Current Feedback Amplifiers (CFAs)

The CFA found its true calling in low gain video line driving and differential xDSL line drivers (ref.1), where DC precision is a minor consideration in, what are often, AC coupled output designs. The architecture does not lend itself well to low nominal output DC errors or drift. Once an amplifier starts to deliver reasonably low nominal 25^{o} C DC errors, the next layer to consider are their drift terms. All CFAs are constructed with a unity gain buffer from the V+ input to the V- input. That buffer will show these DC errors:

- Input offset voltage and drift
- Non-inverting bias current and drift
- Inverting bias current and drift
- CMRR (which arises from the buffer gain being <1.00000).

Even with considerable effort (ref. 2), the best reported input offset voltage drift is a nominal 1μV/^{o} C with a 5μV/^{o} C max., where very few CFAs even specify a max. offset voltage drift. The two input bias currents for a CFA are essentially the difference between base currents arising from mismatched NPN and PNP βs. The mechanisms are completely different at the detail level for the two input bias currents, hence they are unmatched both nominally at 25^{o} C as well as in their temperature drifts. The output DC error drift is often dominated by the inverting bias current drift times the feedback resistor (R_{f} ). Even one of the most recent single channel CFA devices, the THS3491 (ref. 3), specifies only a nominal I_{b} – drift of -116nA/^{o} C (with no min/max – but with the first ever CFA drift histograms, page 17, ref. 3). CFA devices require a narrow range of feedback resistor values (R_{f} ) for stability. Using the THS3491 recommended 576Ω, for the QFN package (Av=+5V/V), translates to 576*(-116nA/^{o} C) = -67μV/^{o} C at the output – hardly a DC precision device. And, since the two input bias currents are not matched in either 25^{o} C nominal nor drift terms, bias current cancellation techniques are not applicable (ref. 4).

Going one more step, the reported CMRR for a CFA device arises from the buffer gain being slightly <1.0000 (ref. 5, page 36). In the four equal-resistor, differential-to-single-ended configuration, it is this slight gain loss across the input stage that gives rise to an output signal when the two inputs are driven from a common mode source. Most CFA input buffers are open loop, where a typical buffer gain of 0.996 would create a CMRR spec of 48dB via equation 1 (with α being buffer gain in V/V).

Stand alone, open loop buffers, specify a DC gain that is very load dependent due to their finite DC output impedance (Ref. 6). The input buffers used in both CFAs, and very high slew rate VFAs (Table 3, Ref. 7), see a no-load condition since the overall loop in both cases drives their output (error) current(s) to zero. The buffer output at the inverting CFA pin cascodes the error current to the current mirrors, while also forcing the inverting node voltage to follow the +V input. Being part of the overall CFA feedback loop means the error current in this buffer output is driven to zero by the high DC loop gain, this is identical to saying the buffer sees a no-load condition. This loop gain induced, no-load condition holds the buffer DC gain very constant vs. external resistor settings at just below 1.000.

This “CMRR” effect in the CFA will “contract” the gain from ideal. This is easy to see in a simple non-inverting unity gain buffer application where the input stage buffer gain reduces the gain from V+ to V- slightly below 1.0000 while the LG/(LG+1) gain compression reduces it slightly more to the output voltage. The four equal-resistor differential-to-single configuration can be used more generally to probe the polarity and magnitude of the error signal across the input stage due to a common mode input voltage swing. This test case produces a very small output voltage swing, reducing the input referred error due to that small V_{out} divided by the Loop Gain (LG), to an inconsequential level relative to the input error produced by the CMRR effect. That CMRR error should produce a +/-μV/V_{cm} input error voltage that then gets gained up by the Noise Gain (NG) to add to the output error (ref. 8).

The test of Figure 1 is driving a 1Hz input square wave into the 4 equal-resistor circuit and is looking for the polarity and magnitude of the square wave at the input error voltage sensing output. This positive first input signal will generate a negative first error signal (including the -1 in the dependent source) if the CMRR effect is a -μV/V_{cm} (or contracting gain) effect – as it is for all CFA devices. This error voltage square wave is sitting on top of the static DC error terms for the low power OPA684 (ref. 9) used in Figure 1. This 1.615mV_{pp} input error swing, for a 1Vpp V_{cm} test signal (at the V+ input pin), gives -20*log(1.615mV/1) = 55.8dB CMRR. This relatively higher CMRR for the OPA684 CFA (vs. a more typical 48dB CMRR) comes from the closed loop input buffer design and approximately agrees with the datasheet specifications. Solving eq. 1 for the buffer gain shows that the OPA684 model is delivering a nominal α=0.9984V/V.

**Figure 1**

**Input error voltage due to CMRR effects in the OP684 CFA simulation model**

While there are no true “precision” CFA op amps, there are better and worse devices. Making a simple sort on maximum 25^{o} C input offset voltage, recognizing very few devices specify a max. offset drift (and many devices physically show an output DC drift dominated by the inverting bias current drift), will yield the rough sort of Table 1. In this range of max. offsets from 2mV to 5mV max, a secondary sort in each offset value ranked them in ascending max. 25^{o} C supply current. In each max. input offset value, this ascending supply current roughly sorts the devices in descending input voltage noise and ascending slew rate. To get newer devices, this table also screened out:

- Max. input Vos > +/-5mV
- Output Headroom >2.0V
- If both disable and non-disable versions, only disable version shown.
- Obsolete devices

**Table 1**

**Single channel CFA sorted by ascending max. input offset voltage.**

Turning back to the very high slew rate VFA devices, using two open loop input buffers (table 3, ref. 7), it might be reasonable to expect those to also show a very slight gain compression (-μV/V_{cm} ) in their simulation models due to the CMRR effect. The transistor based AD8057 (ref. 10) model available in the TINA library (ref. 11) does indeed contract as shown in Figure 2. Many of the more “macromodel”-based devices (in Table 3, ref. 7) show a positive +(-μV/ V_{cm} effect in this same simulation test. This simulated input error voltage swing, of 0.31mV_{pp} for a 1V_{pp} V_{cm} input swing in Figure 2, solves to a 70dB CMRR. This result closely matches the AD8057 CMRR plot (Figure 30, ref. 10) but not the 60dB specification.

**Figure 2**

**Input error voltage due to CMRR effect in a very high slew rate AD8037 VFA simulation model.**

Looking at the other types of high speed VFA devices (ref. 7), it is unclear if they should show a + or – μV/V_{cm} error term and their models seem to essentially give random polarities (where some models have reversed polarities from their original to more recently updated versions). Some sources (slide 9, ref. 12) suggest this CMRR error should be a bipolar Gaussian distribution centered on 0 μV/V. But that implies an average CMRR of infinite dB? There is possibly more modelling work that could be done on this CMRR error term in the wider range of VFA op amps.

**DC Accuracy for High Speed Fully Differential Amplifiers (FDAs)**

These FDAs come in both CFA and VFA types. The CFA-based versions will have phenomenal slew rates but relatively poor DC precision terms. For the wide range of AC-coupled signal path application using CFA-based FDA solutions, this poor DC precision will not matter. The most troublesome term would be the input offset current drift specification – typically a missing spec. for these types of devices. Table 2 shows a thorough DC error specification (ref. 13) that is notably silent on I_{os} drift – likely pretty poor looking at the range on 25^{o} C Input Offset Current.

**Table 2**

**Example DC error specification for the very wideband, CFA based, FDA (the ADA4927, ref. 13)**

Turning now to the more “precision” VFA-based FDA devices (Table 3 below), these have the usual input offset voltage (V_{os} ) and current offset (I_{os} ) errors along with a range of other errors arising from the two feedback networks not being exactly matched – and due to the common mode control loop that is acting to hit a desired output average voltage. Only considering DC issues here, first assume the two feedback resistors and divider ratios to the inputs are exactly matched – as shown in the example of Figure 3 using the precision RRO, NRI THS4551 (ref. 14) with 4 equal 10kΩ resistors and a grounded Vocm input on +/-2.5V supplies. Centered gaussian DC errors (like V_{os} and I_{os} ) are often specified as +/- 1 δ for the typical value. That bipolar value, is then assigned a polarity to include in the nominal simulation model. The full bipolar min/max error range and drifts are available in the datasheets (ref. 14). Figure 3 shows a simple DC setup with measurement probes before the DC simulation in Figure 4 where those numbers will mask the circuit underneath.

**Figure 3**

**Equal R, THS4551 FDA nominal DC error test simulation**

And then running the DC operating point simulation shows these error terms built into the nominal model (ref. 15).

**Figure 4**

**DC operating point errors for the precision THS4551 FDA**

Starting with the common mode voltages, the output common mode shows a +1mV positive offset from the 0V input at the V_{ocm} pin. This matches the magnitude of the typical specification of +/-1mV (ref. 14, page 9). This device is typical in that the common mode control offset error is lower with the input control pin driven vs. when it is floating. The floating input V_{ocm} offset (from mid-supply) is typically +/-2mV on this device. This output CM offset is usually of negligible concern in driving ADCs that show some tolerance on their input common mode voltage range (when specified) far exceeding these <+/-20mV output V_{ocm} errors.

This Negative Rail Input (NRI), PNP input stage device, will have input bias currents that flow out of the input pins. That average value in Figure 4 of 0.9934μA closely matches the typical 1μA in the data sheet (ref. 14, page7). This input bias current specification is uni-polar out of the input pins for this NRI device. One new aspect to the FDA is that this common mode input bias current shifts the “input” common mode voltage from the output common mode that is being controlled by the common mode control loop. The 5.47mV input common mode voltage shown in Figure 4 has shifted up from the 1mV output common mode and correctly splits the available .993μA common mode current into the R_{g2} path to ground, and then the R_{f2} path back to the output 1mV common mode voltage. This input V_{cm} level shift is approximately the output V_{cm} voltage + the input I_{bcm} current times the R_{f} ||R_{g} impedance looking out the two input nodes.

The differential output offset is a combination of the input offset voltage and the effect of mismatched input bias currents (I_{os} ). The nominal +50μV input offset voltage is gained up by the Noise Gain (NG) = 1 +R_{f} /R_{g} to the output while the differential offset current (I_{os} ) adds an I_{os} * R_{f} term to that. Since this I_{os} is differential, the output common mode control loop does not come into play and the typical differential input virtual ground is used to pass this term to the output times just the R_{f} value.

The THS4551 model (ref. 15) sets the typical V_{os} polarity to be a 50μV rise from V+ to V-. This will produce an output of +100μV for V_{o_diff} (Using the (Vo+) – (Vo-) voltmeter in Figure 4). This simulated output offset is then reduced superimposing the nominal model polarity of the I_{os} term. There, the 9nA I_{os} is higher on the non-inverting input pin than the inverting, approximately reducing the 100μV output due to V_{os} by the 9nA*10kΩ ≈ -90μV yielding close to the simulated value of +11μV. Again, the model assigns nominal values and polarities while the full range shown in the datasheet (ref. 14) should be used for output differential offset min/max analysis.

Temperature drifts, on the input bias current average value, will simply shift the input common mode voltage. Temperature drift on the V_{ocm} offset voltage will show up directly as output V_{ocm} drift. Temperature drift on the V_{os} and I_{os} terms will have the same gain as the static values, the NG for V_{os} and R_{f} for I_{os} .

The input stage CMRR is usually high enough to be a minor error contribution in these precision FDAs. The simple test of Figure 5 drives a +/-2V input to matched 1k Ω R_{f} =R_{g} resistors. This will divide down to a +/-1V input Common Mode (CM) swing which produces the very small 3.56μV input error voltage due to CMRR. This error swing calculates out to 115dB CMRR matching the plot (Figure 41, ref. 14) but not the typical 110dB CMRR specification. This small positive +μV/V_{cm} effect then gets to the output times the NG.

**Figure 5**

**Input stage CMRR test circuit using the THS4551 model**

**The effect of mismatched Rs around the FDA on DC precision**

Mismatched resistors around the FDA will add more output DC error terms beyond the simple ones considered thus far. The first to consider is simply the effect of equal standard value feedback R_{f} s, but with some tolerance on their values. Setting up a DC simulation with +/-1% mismatched R_{f} values at a NG of 1, will give the typical output error of Figure 6. Here, the NG = 1 so the output starts with the +50μV V_{os} offset. The 200 Ω mismatch in the feedback R_{f} values gives a differential gain to the I_{bcm} term – a negative going 1μA*200 Ω adding -200μV offset producing the final -150μV shown in Figure 6. The model input offset voltage is shown by (V-) – (V+) probes to equal 50μV. Again, this is simply a nominal value for modeling purposes where the full +/-175μV 25^{o} C max. tested V_{os} range and +/-50nA I_{os} range should be used in output DC error band analysis (ref. 14).

**Figure 6**

**Mismatched Rf test showing output V _{o_diff} shift.**

Moving on to imbalance the feedback divider ratios brings in a range of common mode to differential conversion errors. The conversion gain from any output CM term to the output differential error is shown in Equation 2. Here, G_{1} ≡ R_{f1} /R_{g1} and G_{2} ≡ R_{f2} /R_{g2} in Figure 7 (Equation 2 is algebraically equivalent to the more convoluted expression in ref. 17, page 26)

The test case of Figure 7 can be used to validate this error. Here, a +/-50mV, 1Hz square wave is applied to the V_{ocm} input where, with equal feedback Rs, the G terms are imbalanced with +1% higher ratio the upper path and -1% lower gain on the lower feedback path. Putting those into Equation 2 shows a +0.01 gain for the input V_{ocm} signal – as shown in the output waveform of Figure 7. This 100mV_{pp} input on V_{ocm} appears as a 1mV_{pp} differential error at the output due the feedback ratio mismatch.

**Figure 7**

**Conversion gain from V _{ocm} variation to output differential voltage due to gain mismatch**

This CM to Differential Mode (DM) conversion gain applies to:

- The FDA V
_{ocm}input voltage and drift

- The signal sources’ V
_{icm}voltage and drift

A very common way to generate a poor output static DC differential offset is to imbalance the gain networks when designing for a single supply, single-to-differential, 50 Ω input matched application. Figure 8 shows this typical design using the gain of 1V/V, active impedance solution for a 50 Ω match to a 50 Ωsignal source (Table 2, ref. 14). Here, the gain mismatch is relatively low, but multiplying that by the 2.5V V_{ocm} input voltage on this single +5V supply design predicts a differential output error due to this output offset term of -1.59mV – far exceeding all other initial 25^{o} C differential output offset error terms. The simulation in Figure 8 shows this slightly reduced by the other differential offset terms in the FDA itself. A simple improvement to this built in error is to match the nominal resistor network on the R_{g2} side as seen on the signal input side. Often, this relatively large initial differential output offset can be calibrated out where then the more important terms are the drift effects for each output differential offset contribution.

**Figure 8**

**Output differential offset due to gain imbalance and input V _{ocm} voltage.**

This CM to DM conversion gain can have both a static error due to standard value selections, and then a spread due to resistor tolerancing, and a spread plus drift due to the V_{ocm} input tolerance and drift through to the output CM voltage. Often, this V_{ocm} based output differential offset “drift” term will be negligible relative to the input offset voltage drift term times the noise gain. Using the maximum +/-10μV/^{o} C CM offset drift for the THS4551 (ref. 14), and the conversion gain of Figure 8, only gives an output differential drift of .0063μV/^{o} C. While the nominal output differential offset can often be dominated by this V_{ocm} input times the gain imbalance conversion gain, its drift contribution can often be neglected where the input offset voltage drift times the noise gain normally dominates the output differential offset drift.

The effect of input common mode bias current (I_{bcm} ), combined with resistor imbalances, is a new error source in all VFA based FDAs. Briefly, the I_{bcm} term will first generate an added output differential offset due to mismatched R_{f} values. Also, this I_{bcm} times the average impedance looking out of each input (R_{f} ||R_{g} ) will generate a shift in the input common mode voltage (the output CM control loop pushes this error to the input pin CM voltages). That voltage will then generate an output differential error times the (G_{1} -G_{2} ) terms described earlier. These same gains will apply to the I_{bcm} drift error term.

Recent FDA introductions have vastly improved on the input stage DC error terms. Table 3 shows a range of these solutions sorted in ascending 25^{o} C maximum input offset voltage. To limit these single channel selections, the following were also screened out:

- Max 25
^{o}C input offset voltage >1.5mV

- 1k MSRP > $4.00

- Obsolete devices

Note there are a few G_{min} >1 devices indicating a de-compensated design where lower input voltage noise with higher slew rate is usually the intent. A G_{min} = 1V/V in this FDA case would be a DC NG=2. This sometimes means a low phase margin condition can be experienced with simple bandlimiting feedback capacitors – taking the NG to 1V/V at higher frequencies (ref. 16).

**Table 3**

**Single Channel, Precision, VFA based FDA devices**

CFAs (and CFA based FDA devices) will not be able to provide good DC precision. Beyond the dominant error terms from relatively high input offset voltage drift and mismatched input bias current terms, the CFA will have a CMRR effect that will look like a negative μV/V_{cm} input error for a non-inverting gain configuration. This will act to compress the non-inverting gain from ideal (with a similar effect likely in the very high slew rate VFA topology using two open loop input buffers).

VFA based FDAs start out with the usual input offset voltage and offset current errors, but then add a myriad of static and drift errors due to mismatched resistor networks on the two sides. Often, that mismatch will deliver the dominant static error through the desired V_{ocm} voltage, but rarely a meaningful drift term. Some recent permutations to the LTC6363 FDA (ref. 17) have added precision on chip resistors to reduce these resistor mismatch errors in fixed gain alternatives. Next up – high speed amplifier stability issues!! More commonly known as the full employment program for high speed amplifier application engineers!!

**References for DC errors in high speed CFA and FDA amplifiers**

- Input and Output Voltage Range Issues for High Speed CFAs and FDAs, Insight #2, Michael Steffes, Planet Analog, 10/27/2018

- ADI, AD844, Quad, 60MHz, 2000V/μsec, Monolithic Op Amp

- TI, THS3491, “900MHz, 500mA High Power Output Current Feedback Amplifier”

- “ Op Amp Total Output Offset Calculation”, ADI app. Note MT-39

- TI, OPA695, “Ultra-Wideband, Current Feedback Operational Amplifier with Disable”

- TI, BUF634, “250mA, High Speed Buffer”.

- DC precision considerations for high speed amplifiers, Insight #3, Planet Analog, “DC Precision Considerations for High Speed Amplifiers”, Michael Steffes, 11/15/2018.

- – ADI app. Note MT-042, Op Amp Common Mode Rejection Ratio .

- TI, OPA684, “Low Power, Current Feedback Operational Amplifier with Disable”

- ADI, AD8057, “Low Cost, High Performance, Voltage Feedback, 325Mhz Amplifier”

- TINA simulator available from DesignSoft for <$350 for the Basic Plus edition. Includes a wide range of vendor op amps and is the standard platform for TI op amp models.

- TI Precision Labs Training, CMRR, TIPL-1231

- ADI, ADA4927, “Ultralow Distortion, Current Feedback Differential ADC Driver”

- TI, THS4551, “Low Noise, Precision, 150MHz Fully Differential Amplifier”

- Extracting Loop Gain and Phase Information from Simulation, Planet Analog, “Extracting Loop Gain and Phase Information from Simulation”, Michael Steffes, Aug. 9, 2018

- LTC, LTC6363, “Precision, Low Power, Differential Amplifier/ADC Driver Family”

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