Debunking myths about analog IP at 28 nm

The economics of system-on-chip development are objective and well understood. Industry-wide trends set the stage for integrating more functions into a SoC, which then drives the scaling down of process technology nodes. In the resulting product, all of the previous product’s functionality is implemented while more functional blocks are added to build increasingly complex functionality. This trend is not questioned – it is an axiom.

Register transfer logic (RTL) is agnostic to the process technology node, so porting digital functionality is not perceived as problematic. However, analog functionality is perceived as more challenging because of its closer dependency on the process characteristics. At each new node, the debate regarding whether or not to integrate analog IP into the SoC is rekindled until the economics validate the integration. Successful mixed-signal SoCs in all previous process technology nodes have demonstrated this cycle despite the persistence of three myths around the economics of analog block implementation in advanced process technologies.

These three myths deserve to be analyzed to better understand why they are erroneous.

Myth #1: The economics of analog integration don’t add up
Analog circuitry does not scale in the same way as digital circuitry. The performance requirements for analog blocks, especially in terms of linearity, mean the function is easier to implement using thick oxide devices at I/O supply level. As this type of device has not changed in many generations, the total area of the analog block that uses it is also more or less constant.

In this case, the myth is that the relative portion of the real estate allocated for the same function in new process technologies keeps increasing, and therefore the cost also increases to a point where integrating the analog function is no longer justified.

Advances in analog circuit techniques disprove this myth. For example, digitally assisted analog architectures, digitally calibrated architectures, and other dithering and randomization techniques can, through digital processing, eliminate most of the non-idealities inherent to deep-submicron devices. This simplifies the circuit, making it more robust and increasing performance while using only thin-oxide devices.

By reducing analog complexity and taking full advantage of process characteristics, the economics of integration are positive to analog block integration. Most designers find that integrating these blocks end up improving their competitive position in the market.

Myth #2: Integrating analog IP is too risky

Given the huge costs for developing new products at advanced process technology nodes, risk mitigation is a very important factor to consider when deciding what approach to use. Analog blocks are often judged to be too immature and risky for integration in new process technologies.

Advanced process technology nodes pose new challenges to the development of integrated circuits. In particular, some performance characteristics of analog blocks rely on specific process characteristics. For example, device matching and output impedance suffer larger variations due to layout-dependent effects such as well proximity effect (WPE) and shallow trench isolation (STI) stress. These and other ageing effects are prevalent on advanced process technology nodes and can degrade circuit performance. All of these effects must be taken into account during the architecture and design phases.

However, digitally assisted analog architectures alleviate the performance issues and make these blocks less sensitive to process effects. In addition, thorough design validation flows ensure that all effects are accounted for during the design phase.

System architects minimize the risk of system implementation by using pre-validated IP blocks from trusted IP partners. The partners they choose must understand the design requirements and have the capability to implement heavy, tool-intensive design validation flows and provide silicon-validated IP in advanced nodes.
As the cost of the fabrication increases, system architects find the argument to include pre-validated analog and mixed-signal IP even more compelling. The economic tradeoff associated with using an existing IP block that has adequate characteristics is largely compensated for by the ability to mitigate the risk through silicon validation.

Myth #3: Analog IP development cycles are incompatible with time-to-market windows

In advanced process technology nodes, design validation flows and system development cycles are lengthy and tool-intensive. Thousands of simulation runs are necessary to cover all corner and functional cases, including statistical variations. This extensive, but necessary, validation process can impact time-to-market of a product, which propagates the myth that integrating analog IP will delay a product’s time to market. The pervasiveness of this myth highlights the importance of using off-the-shelf analog IP.

Re-usable analog IP blocks should be both generic, to cover wide range of applications, and specific, to limit any cost penalty to the system due to over-specification. These apparently incompatible constraints are addressed by implementing configurable analog IP blocks.

Configurable IP relies on the deployment of a complete set of sub-blocks that are validated together. This set of sub-blocks can be optionally implemented or left out depending on the system requirements. Designers can use validated groups of sub-blocks to configure a final product that matches the requirements of the system. As analog IP typically is used as physical hard macro, the sub-blocks seamlessly abut without adding risk. This is illustrated in Figure 1, where two specific configurations of the analog-to-digital converter (ADC) core –one including optional complex functionality and the other including an input buffer–are obtained by combining optional blocks that are pre-validated together.

Click on image to enlarge.

Figure 1: Configurable ADC from validated sub-blocks

Synopsys has applied the concept of configurable analog IP to several classes of products ranging from high-performance DesignWare Data Converters to complete analog front-ends and audio codec sub-systems. In these products, characteristics such as the number of channels and the type of analog interface and drivers can be configured. This IP enables designers to create validated analog IP products that match their specific requirements.

Since SoC designers validate configurable analog sub-blocks together with no new design needed, the development time is minimal. They validate the final design, ensuring that it offers effective area use and power dissipation for each system’s needs. Using configurable IP makes integration of analog IP easier due to the short time to market, and it also significantly reduces the risk.

About the author
Manuel Mota is Technical Marketing Manager for Data Converter IP within the Solutions Group at Synopsys. Mota has worked in the semiconductor industry for more than 10 years as analog IP designer for Chipidea Microelectronica (Portugal) with responsibility for the design of PLL and Data Conversion IP cores as well as complete Analog Front-Ends for communications. He holds a PhD in Electronic Engineering from the Lisbon Technical University which he completed while working at CERN (Switzerland) as a Research Fellow.

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