[Editor's note : we are presenting this lengthy, insightful article in four parts:
- Part 1 looks at driving high-performance, high-speed ADCs, and benefits to using an input transformer in a differential inverting amplifier design
- Part 2 looks at adding an interstage filter between the amplifier and the ADC
- Part 3 looks at managing SFDR degradation in a low-power interface, and provides and example of broadband, low-power design with tested performance
- Part 4 provides measured results for the test circuit
Also, for convenience , the extensive references for all four parts are repeated as a group at the end of each part.]
Adding an interstage filter between the amplifier and the ADC
While ADC characterization will often show transformers as the sole passive elements required for implementation, what is always in front of those transformers is a narrowband, tuneable bandpass (BP) filter that strips off the source spurious and broadband noise before the FFT is taken.
Real implementations usually have some aggressive “Nyquist” filtering at lower power levels before the last stage and then this last stage of gain. The Nyquist filter is usually not right at the ADC inputs, due to the significant insertion loss normally taken in these more aggressive filters. If the Nyquist filter were last, for instance, and had even only an 8dB insertion loss, a 2Vpp full=scale input to the ADC would then require a 5Vpp at the input to the filter.
This immediately pushes the design into much-higher power= and supply=voltage amplifiers just to drive this filter. Placing the Nyquist filter before the last stage allows more modest power levels to be applied to its inputs where the insertion loss is then recovered in this last amplifier stage.
But now, we have a very broadband amplifiers’ output noise that must be bandlimited in some fashion, before the ADC folds it all into the Nyquist band at the FFT output. This noise filtering requirement is not intended to provide Nyquist filtering, but rather to get the full benefit of a very broadband amplifier for its harmonic distortion performance, but control the integrated noise added by this stage before it is digitized at the ADC.
Depending on the final SNR targets, a simple RC filter may be adequate. Usually this filter must also remain flat through the intended frequency band. Doing that with an RC filter pushes its F-3dB cuttoff well above the desired frequency span.
Further, converting a single RC pole bandwidth to “Noise Power Bandwidth” is a 1.54× multiplier. Often, just going to a simple 2nd order RLC filter can greatly reduce the integrated noise power available from this last stage over the simple RC filter. Let’s continue the example above stepping from no filtering, simple RC, and then an RLC 2nd order low pass example.
With a 7.3nV/√Hz differential output noise what RMS noise will be delivered to the ADC inputs using different interstage filters?
A. No filtering, assume the noise will be bandlimited by the ADC input bandwidth. The 4GHz Gain Bandwidth of the ISL55210 would suggest a 4GHz/3 = 1.33GHz closed loop bandwidth. Remember, the noise gain is 3 in the circuit of Figure 1 with 50? source, Rg = 50? and Rf = 400?, as the source resistor is modeled as splitting on each side of the transformer secondary to add another 50? to Rg in calculating the noise gain. In fact, the ISL55210 will be >2GHz so the real bandwidth up to the ADC inputs will probably be set by the input transformer.
Let’s use a 1GHz estimate for the amplifier and/or ADC self=limiting bandwidth for noise-calculation purposes. Assuming that the integrated (or RMS) noise coming from this 7.3nV/√Hz just due to the ISL55210 will be given by Equation 5 – this evaluates to 287µV RMS noise .
(converting single pole -3dB to noise power bandwidth and getting integrated noise)
B. Target a simple interstage-RC filter with some bandwidth and flatness. For example, target a 0.5dB flatness through 150MHz. Equation 6 shows the calculation for F-3dB if a certain attenuation (γ) is targeted at a lower frequency. This -0.5dB target is trying to set a γ = 0.944. Putting that into Eq. 6 with the target rolloff frequency at 150MHz, gives a target F-3dB for the RC interstage filter of 616MHz. Using this in Equation 5 gives a reduced integrated noise up to the ADC of 225µV RMS noise.
(required F-3dB target to hit some gain <1 for a single-pole RC filter at Ftarget)
C. Now target a 2nd order interstage filter with ±0.5dB flatness through 150MHz. This filter would be implemented as a series R followed by a series L on each output, then terminated with shunt R and C to include both the ADC input impedance and the required external R and C to get the filter.
An easy way to get the required Fo and Q for this filter would be to use a filter design tool and recognize this is a 2nd order, 0.5dB ripple, Chebychev definition. It is important to use a tool that is defining the Chebychev as the exit from the allowed ripple band (Reference 4 does this) Using the tool of Reference 4, or going to Chebychev polynomial tables, shows we need to target Fo = 185MHz with a Q of 0.864, which results in an F-3dB of 1.39×150MHz = 209MHz.
From here, we need to convert the frequency response shape into a noise power bandwidth. This is given in Equation 7 (from Reference 5 , page 4). Evaluating this for the 0.5dB flatness filter through 150MHz gives 251MHz for a noise power bandwidth using the target Fo = 185MHz and Q = 0.864. Taking the square root of this NPB times the 7.3nV/√Hz spot noise gives an integrated noise of 116µV RMS to the ADC inputs.
(noise power bandwidth for 2nd order low pass filter)
As expected , moving from no filter to a 2nd order filter has greatly reduced the integrated noise contributed by this last stage interface from 287µV to 116µV RMS. But what does this mean for the combined ADC plus amplifier SNR? The SNR coming into the ADC will combine with the SNR for the ADC by itself in an RMS sense given by Equation 8 :
One complexity in using Equation 8 is we have to use the right SNR for the ADC and then the correct signal level for what is being delivered to the inputs. Many ADCs test and report an SNR at 1dB below the full-scale input range to avoid clipping (-1dBFS ) but then also report an SNRFS where they have added 1dB back to the measured number, to give a theoretical SNR if the converter were successfully driven to the last possible code on each end (Full Scale, dBFS ). To be consistent, we much choose one then work to the “signal” level delivered to the input pins at the same level. We will use the -1dBFS SNR number here.
The integrated noise numbers for the three test cases above are so low that no meaningful degradation in SNR will be seen until the ADC itself is >70dB SNR. Continuing our examples with an actual ADC, the ISLA214P50 (a 14bit, 500MSPS low=power ADC), we can pull a typical SNR from its data sheet at 105MHz single-tone input as being 72.6dBc dBFS, or 71.6dBc at -1dBFS.
The full-scale input for this converter is a differential 2Vpp so the -1dBFS swing will be 1.78Vpp. To form the SNR at the input pins, we need the RMS voltage of this -1dBFS signal. That will be given by Equation 9 where evaluating this for 1.78Vpp gives a 0.63Vrms.
(single-tone sinusoidal Vpp to Vrms conversion)
To develop an input signal SNR, we must compare the single tone -1dBFS RMS single level to the integrated RMS noise delivered to the input pins from the interface. Then, with that SNR at the input pins, we can use Equation 8 to predict the resulting FFT SNR if the amplifier input is driven with a narrowband filtered test tone at 105MHz. The RLC filter results need to be adjusted for any insertion loss in this filter but those will be slight.
Also, these filters need to be implemented with series R values ≤50Ω to keep their noise contributions from increasing the estimated differential output noise. For instance, using two 100Ω series resistors to implement the RC filter will add the noise contribution shown in Equation 10 to the calculated differential output spot noise of the FDA.
RMSing this with the 7.3nV spot noise in this example raises the spot noise that gets into the filtering (if any) to 7.5nV spot noise. This is not a big change using 100Ω, but it can start to be an issue if higher values are used.
Table 1 summarizes these results stepping from no filtering to a 2nd order RLC filter where the combined SNR is RMSing the SNR up to the ADC input pins with the ISLA214P50 -1dBFS SNR typical of 71.6dBc.
Table 1. Comparison of combined SNR with different interstage filters
With the most noise-bandwidth control using the 2nd order filter, we see only a 1.6dB drop in combined SNR. Clearly no filtering it going to reduce the SNR significantly, while a simple RC is better, going to the RLC has improved the predicted SNR 4dB in this case.
This type of calculation can be done for any amplifier + filter + ADC combination. The results here are extremely good for a 150MHz interstage filter, as the total output noise for the example circuit is only 7.3nV/√Hz. This comes from a combination of a very low noise amplifier with the noise benefits of the input transformer topology of Figure 1.
This type of analysis is really intended to explain the resulting SNR for test circuits that are still preceding this last gain plus filter stage with a narrowband BP filter. Most systems have an already dominate noise spectrum coming into this last stage amplifier where the main interest is that this stage does not make it any worse. The example amplifier here is <1nV/√Hz input referred noise which will probably be well below any real spectrum delivered at the input in an actual system environment.
Another way to use Equation 8 is to plot it as a degradation from any ADC SNR, given an input signal that has an SNR ≥ the ADC. This shows the asymptotic nature of this combination. Increasingly better input SNR can approach, but not meet, the original ADC specification. Figure 4 shows this plot which can be applied to any ADC and/or input SNR.
Figure 4. Normalized SNR degradation plot
Starting at an input SNR matching the ADC (0dB on the x-axis above), we see a -3dB degradation should be expected. Conversely, if the goal is no more than a 0.5dB degradation, then the input must be >9dB better than the ADC itself. These sorts of targets really imply a close attention to the benefits of interstage filtering.
[end of part 2]
1. “Simple Circuit Techniques Yield High-Dynamic Range Amplifier”, Electronic Design Analog Applications Issue, June22, 1998 pp22-33.
2. ISL55210 data sheet. http://www.intersil.com/data/fn/fn7811.pdf
3. Contact the author for the NF derivation using two op amps in the input transformer coupled differential inverting design.
4. Intersil “Active Filter Designer” http://web.transim.com/iSimFilter/Pages/DesignReq.aspx
5. “Noise Analysis for High Speed Op Amps” TI application note SBOA066A, 1996, Michael Steffes
6. ISL112P50 data sheet. http://www.intersil.com/data/fn/fn7604.pdf
7. “How RF Transformers Work” Mini-Circuits application note http://www.minicircuits.com/pages/pdfs/howxfmerwork.pdf
8. “Spice model simulates broadband transformer”, Michael Steffes EDN Design Ideas, May 11, 1995 pp135-136.
9. Contact author for a copy of the ADT4-1WT model that can be used with Intersil’s iSim PE simulator.
About the author
Michael Steffes is Senior Applications Manager, Intersil Corp.with more than 25 years of experience in high-speed amplifier design, applications, and marketing.Previously, he wasthe Market Development Manager for High-Speed Signal Conditioning, and a Distinguished Member of the Technical Staff, at Texas Instruments Inc. With more than 25 years of experience in high-speed amplifier design, applications, and marketing, Michael currently provides product definition and customer design-in support.
Michael earned a BSEE from the University of Kansas and an MBA from Colorado State University. He shares several basic patents in high-speed op amp designs and has written more than 85 product data sheets, scores of contributed articles, applications notes and conference papers.