*[Editor's note * : we are presenting this lengthy, insightful article in four parts:

- Part 1 looks at driving high-performance, high-speed ADCs, and benefits to using an input transformer in a differential inverting amplifier design
- Part 2 looks at adding an interstage filter between the amplifier and the ADC
- Part 3 looks at managing SFDR degradation in a low-power interface, and provides and example of broadband, low-power design with tested performance
- Part 4 provides measured results for the test circuit

*Also, for convenience * , the extensive references for all four parts are repeated as a group at the end of each part.]

**Managing SFDR degradation in a low-power interface **

The input interface of Figure 1 already provides significant even- and odd-order HD suppression. The balanced differential signal path leads to lower HD2 and IMD2 term, at far lower power than many alternate structures. The slight loop-gain benefit of the input transformer also lowers all terms slightly from more typical interfaces.

At the output, there will still be even- and odd-order harmonics as well as intermodulation terms. The most challenging of course are the two-tone IM3 terms, which will often fall in band for any interstage filters. The HD2, IMD2 and HD3 terms can benefit from some interstage filtering as the desired signal frequencies to the ADC start to produce those harmonics above the cutoff band of the interstage filter.

For the amplifier itself, the distortion terms at the output are strongly influenced by the voltage and current demands on the output stage. Ideally, the interstage filter will look like a high impedance to the amplifier, while the ADC prefers a low source impedance. In this differential inverting design, the two feedback resistors combine in parallel with the output load as part of the total load impedance. For noise, we would like the feedback resistors to be as low as possible. This must be balanced by their contribution to SFDR degradation due to loading effects.

For the AC-coupled input example designs shown here, it is also useful to consider an output DC-blocking capacitor to allow an easy means to level shift the FDA output common-mode voltage to the Vcm required by the ADC. Often, the FDA will have an internal default output Vcm setting that optimizes the FDA linearity while the ADC will have its own.

These can sometimes be the same voltage (relative to ground – all modern ADCs are single supply), but they are often different values. Further, with the continued progress in low power ADC designs, with the continued reduction in supply voltage that comes with finer geometry processes, these lower-voltage, higher-performance ADCs often have a smaller allowed variation in the applied Vcm voltage for the two inputs. If possible, going AC coupled as part of the output filter design allows both of these issues to be easily managed.

**Figure 5 ** shows one possible interstage filter that includes both a 2^{nd} order low-pass filter design and simple Vcm management. In this example, the low power 12-bit, 500MSPS ISLA112P50 is shown where the unique input stage of that device requires a clock-dependent common-mode input current, shown in Figure 5 as Icm. Vb is set to account for that Icm current through the Rt resistor to match the required input Vcm voltage for the ADC.

*Figure 5. Example output stage interface including a 2 ^{nd} order low-pass with simple Vcm setup. *

The filter design must include the internal ADC shunt resistance and capacitance. In this single-supply example, the output Vcm for the FDA is defaulting to an internally set 1.2V level, while the ADC is looking for a 0.535V nominal Vcm setting. The Cb blocking element handles that level shift very nicely, while retaining a very broadband interface on the low-frequency side. Setting Cb to 1µF will normally set the high-pass pole of the output interface below the low frequency cutoff of the input-side transformer of Figure 1 (not shown here).

Assuming we can deliver a very-high SFDR spectrum, with a controlled noise-power bandwidth, using the interface of Figure 5, how do those distortion terms at the input of the ADC combine with the ADC generated terms to produce the SFDR in the output FFT? To a first order, they combine linearly giving a significant reduction in the combined SFDR, if not well below the specified ADC SFDR specifications.

This simple vector addition of the spurious terms is given in SFDR terms by **Equation 11** .

(Eq.11 Combined SFDR in the FFT, given the ADC spec and the SFDR at the input of the ADC.)

This equation needs to be used on a tone-by-tone basis. But, usually, there is a dominant term that will set the SFDR in the FFT. It is perhaps best to re-cast this expression in terms of degradation from ADC spec given an input signal that is some number of dB lower than the ADC.

**Figure 6 ** shows this normalized curve where the x-axis is design margin coming into the ADC inputs while the y-axis is dB of degradation from the ADC specification.

*Figure 6. Normalized SFDR degradation plot. *

This curve can be used for any ADC to understand the loss of SFDR given some level of SFDR up to the ADC input pins. Or, conversely, having observed what looks like a loss of SFDR performance in a full interface design (and again, we are testing this last stage interface with a very narrow-band single- or two-tone test signal that has a lab BP filter to control the input spurious – just at a much lower power level out of that filter into this last gain stage) we can work backwards to infer the input signal spurious that would explain the degradation.

When the input-signal spurious equals the specified ADC SFDR, we should expect a 6dB (vs. 3dB on SNR) SFDR loss in the output FFT. Conversely, if setting out to limit the ADC degradation in this last stage interface to <1dB, Figure 6 would suggest the input signal needs to be >19dB lower distortion than the ADC specification.

Most designs are somewhere in between, but it is important to recognize that there is no low-power, broadband, solution that can limit the degradation to 0dB. Unlike noise, we cannot easily predict the HD performance up to the ADC inputs, but we can measure the output FFT and infer from Figure 6 what it must have been if we assume typical ADC performance.

**Example: broadband, low-power design with tested performance **

To test these options, an example design using the 115mW ISL55210 and the <500mW ISLA112P50 ADC will be shown. Here, an input transformer with a 1:2 turns ratio was used and an output side filter targeting a flat response through 120MHz was the intended target. **Figure 7** shows the test circuit.

Figure 7. Broadband test interface design

The input 1:2 turns ratio is seeing an input 50? match using the two 100? gain resistors going into the FDA summing junctions (see sidebar on wideband transformers, at the end of Part 4). The gain is tuned with the feedback resistors then and here it is set to 4.95V/V in the amplifier or about 10V/V (20dB) including the input transformer. To understand the output filter interface, we need a few of the ISLA112P50 input specifications (**Reference 6** )

Rin = 500Ω (differential)

Cin = 1.9pF (differential)

Icm = 2.6µA/MHz (each input, dependent on sample rate)

Full scale input is:

1.45Vpp (-1dBFS is then 0.89×1.45Vpp = 1.29Vpp)

105MHz AC specification (typical)

SNR at -1dBFS and 105MHz input = 64.9dBc

HD2 /HD3 at 105MHz = -91/-86 dBc (Figure 5, Reference 6)

So including those internal ADC impedances and looking at the RLC filter single ended gives the following elements (neglecting the blocking capacitor)

Rs = 40.2?

L = 33nH

Rp = 210||250 = 114Ω

Cp = 20pF + 3.8pF = 23.8pF

To extract the interstage filter characteristics, we first work single ended. If we define the total load impedance as Rs +Rp = Rt and the low frequency attenuation as λ = (Rp/(Rt) the resulting ω_{0} and Q expressions for this filter are given as **Equation 12** and **Equation 13** :

Putting in numbers from above

Rt = 40.2 + 114 = 154.2Ω (2× this will be the differential load at low frequencies)

λ = 114/154.2 = .74 (-2.62dB insertion loss from amplifier to ADC)

Fo = 209MHz

Q = 0.82

Including a 0.4dB insertion loss in the input transformer along with this 2.62dB midband insertion loss for this filter, the total circuit should provide 20dB -0.4dB-2.62dB = 17dB gain and this is very close to the measured value.

Going back to Equation 7, this interface should be giving about 271MHz noise power bandwidth.

Now, to estimate the SNR delivered to the ADC input, go back to Figure 3 for the output spot noise for just the ISL55210, at a gain of 20dB. On the 1:2 input turns ratio curve, we see about 0.9nV. Since this was a NF derived curve, it is not including the source 50? which will add a broadband noise source – adding this to be conservative (the source here is a BP filter with some output attenuator) will give a total input noise of 1.27nV. Multiply this by the expected midband gain to the ADC of 17dB (7.08V/V) to get 6.33nV/√Hz for use in the integrated noise equation. The estimated integrated noise at the ADC inputs will be given by **Equation 14** .

Assuming we produce -1dBFS input signal at the ADC input of 1.3Vpp (which will be 1.76Vpp at the amplifier output pins including the filter insertion loss of 0.74), the Vrms voltage for the 105MHz test frequency will be 0.46Vrms using Equation 9. This then predicts an input SNR of 72.9dB at the ADC inputs during a -1dBFS test.

Then, using Equation 8 and the 64.9dBc SNR for the ADC at -1dBFS at 105MHz input, we should see an output SNR in the FFT of 64.3dB (this is a 0.6dB degradation at the -1dBFS specified point). The output SFDR is difficult to predict. But looking at the results, and using Figure 6, an estimate can be made of what was getting to the ADC input pins.

**[End of Part 3] **

**References **

1. “Simple Circuit Techniques Yield High-Dynamic Range Amplifier”, Electronic Design Analog Applications Issue, June22, 1998 pp22-33.

2. ISL55210 data sheet. http://www.intersil.com/data/fn/fn7811.pdf

3. Contact the author for the NF derivation using two op amps in the input transformer coupled differential inverting design.

4. Intersil “Active Filter Designer” http://web.transim.com/iSimFilter/Pages/DesignReq.aspx

5. “Noise Analysis for High Speed Op Amps” TI application note SBOA066A, 1996, Michael Steffes

6. ISL112P50 data sheet. http://www.intersil.com/data/fn/fn7604.pdf

7. “How RF Transformers Work” Mini-Circuits application note http://www.minicircuits.com/pages/pdfs/howxfmerwork.pdf

8. “Spice model simulates broadband transformer”, Michael Steffes EDN Design Ideas, May 11, 1995 pp135-136.

9. Contact author for a copy of the ADT4-1WT model that can be used with Intersil’s iSim PE simulator.

**About the author **

** Michael Steffes ** is Senior Applications Manager, Intersil Corp.with more than 25 years of experience in high-speed amplifier design, applications, and marketing.Previously, he wasthe Market Development Manager for High-Speed Signal Conditioning, and a Distinguished Member of the Technical Staff, at Texas Instruments Inc. With more than 25 years of experience in high-speed amplifier design, applications, and marketing, Michael currently provides product definition and customer design-in support.

Michael earned a BSEE from the University of Kansas and an MBA from Colorado State University. He shares several basic patents in high-speed op amp designs and has written more than 85 product data sheets, scores of contributed articles, applications notes and conference papers.

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