This month we have guest blogger Joseph Wu from TI
Designing with a delta-sigma analog-to-digital converter can help achieve the highest possible resolution in your system. But to maximize this architecture’s benefits, it helps to understand how the delta-sigma modulator and digital filter in the ADC combine to achieve greater measurement resolution. On the Precision Hub blog on the TI E2E Community, I explained that the analog-to-digital converter (ADC) is constructed from a ΔΣ modulator and digital filter.
Using the delta-sigma (ΔΣ) modulator, the ADC converts the input into a digital pulse stream with a 1’s density proportional to the input divided by the reference. Let’s take a practical example to show how the digital filter converts the pulse stream into a data word representing the conversion. (For more on how the delta-sigma ADC is constructed or how the modulator works, see my recent Precision Hub post on the TI E2E Community).
Figure 1 shows a modulator. Let’s set the input to 0.15V and the reference to 1V so that the input range is +/-1V. After running the modulator for seven cycles, the bitstream will look something like Figure 1:
If you add the number of times the modulator output became a 1, you would get as few as zero and as many as seven, with eight possible outcomes. The digital filter accumulates the modulator outputs over a number of modulator cycles to produce a digital representation of the input. If you plot the transfer function of the modulator output, it would look like Figure 2:
With a full-scale range from -1V to 1V and eight possible outputs, the least-significant-bit (LSB) size is 0.25V, as shown in the step size in Figure 1. Using the transfer function of the modulator, you can construct the output in Table 1:
Since the modulator output contains four 1s, this would correspond to a quantization value of 0V and a three-bit output code of 100.
If you extend the modulator output run for the next eight outputs for a total of 15 cycles, you would have the output shown in Figure 3:
Using 15 modulator cycles, we divide the full-scale range from -1V to 1V into 16 equal parts, giving an LSB size of 0.125V per bit. This is shown in Figure 3 and Table 2:
Accumulating the first 15 pulses, you get nine 1s and a quantization value of 0.125V, with a four-bit output code of 1001.
In both examples, we oversample the input at a higher frequency and put out a data word at a lower data rate. In the first example, we sample the input voltage seven times to get one data word of three bits (from 23 -1 pulses). In the second example, we sample the input voltage 15 times to get one data word of four bits (from 24 -1 pulses). With more modulator iterations, we will get a result with more resolution but at a slower data rate.
When we change the data output rate, we change the digital filter to collect a different amount of modulator outputs. Digital filters can have different implementations with weighted averaging and convolution over multiple samples. With higher-order modulators, we can get more resolution with fewer modulator samples. With more modulator samples, we lower the frequency of the filter and increase the output resolution.
That’s how a basic ΔΣ data converter works. The modulation will take the quantization noise and shape it to have higher-frequency content. The digital filter removes high frequency noise while retaining the original input signal. The modulator and digital filter combine to give high-resolution measurements by oversampling the input. With a small sacrifice of speed, we can achieve greater resolution in the measurement.
Click here to learn more about the benefits and applications of the high-resolution delta-sigma ADC architecture.
For more in-depth information, see the following resources:
TI’s broad range of delta-sigma ADCs with resolutions ranging from 12 to 24 bits and speeds from 5SPS to 10MSPS