All present-day communications gear needs accurate frequency sources with low phase noise for the transmitter. An accurate frequency source is also needed for the receiver for the local oscillator that's part of the superhetrodyne circuitry. And if the com-gear is a cellphone, a tablet device, or similar battery operated device, that frequency source must be very low power. You could use a crystal for a frequency source. It would be stable and clean.
However, these devices typically need additional frequency sources for the digital and data transmission portions. That would include, but not be limited to, MCUs, DSPs, FPGAs, and ASICs. Pretty soon, you'd be using lots of crystals and lots of PC board space. Anything that could be done to tie some of these clocks together should help. That would mean synchronizing them or using a common master clock to synthesize the other frequencies. For frequency synthesis, we would need a PLL (phase locked loop) or better yet, a DLL (digitally locked loop).
A recent paper published as part of the IEEE's ISSCC conference discusses a new IC design for a multiplying DLL (MDLL). An MDLL forms the heart of a frequency synthesizer. The device can operate with a supply voltage of 0.45V and uses 423nW of power. Clearly, the designers had the handheld devices in mind with this IC.
With an MDLL, you still need other (mostly) free-running oscillators that are synchronized to the master clock (the crystal oscillator). Those need to be low power and they should use as little PC board space as possible. Again, the designers of this IC found a clever way to implement this.
Starting conceptually with an RC network, they note that for some arbitrary low frequency, you would need either a large R and a small C or vice-versa. Power draw would be smaller with the large R version, so the designers proceeded from there. Rather than trying to fabricate very large value resistors in silicon, and in consideration of the need for controllability, the designers took a different approach. They substituted a P-channel FET functioning as a current source for the resistor. They used the leakage characteristics of the FET with the drain either grounded or at the (+) supply potential (switchable).
(Source: See Reference 1)
This is the heart of their digitally controlled oscillator. They use a number of these FET-capacitor networks to create the MDLL. The reference frequency is taken from a 32kHz crystal oscillator.
The measured phase noise looks to be pretty good. Here is the empirical test results with N=100 (i.e., fOUT = 3.2MHz):
It's under these conditions that the designers measured the power draw of 423nW. The phase noise shows rejection of the in-band noise below 32kHz. The out-of-band noise is -95dBc/Hz at 1MHz offset.
The device is implemented in a 65 nm CMOS and the core area is 0.026 mm2 . Let us know if you have any applications for an IC like this.
1. A 0.45V 423nW 3.2MHz Multiplying DLL with Leakage-Based Oscillator for Ultra-Low-Power Sensor Platforms. Authors: Dong-Woo Jee, Dennis Sylvester, David Blaauw, and Jae-Yoon Sim
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