Design Margins in Analog & Digital

Design Margin is a term that engineers use, sometimes rather casually, when describing how “close to the edge” a design is. The margin might relate to power dissipation in a component or the voltage applied to a device with respect to its absolute maximum rating. Sometimes the margin is a nebulous quantity and it isn't clear how much margin exists above a customer supplied specification. For someone doing a design, this can be a significant problem. It takes a significant amount of study and analysis to determine the true design margins that are required. As designers, we often find that to do a given function requires significantly more margin than what the customer assumed (based on their specifications).

This can be especially true for RF susceptibility. For example, assume that someone is doing a design related to a fuel system that may be subject to an RF field of strength to be specified during the design process. The customer may supply a specification that is boiler plate from all their other designs. At first look, it may seem fine. However, upon further study, one may determine that RF from more than one source can combine to cause components to heat to a flash point. This is very different from RF jamming a single susceptible channel or IF. This can mean that significant margin can be required to truly be safe. Furthermore, foreign countries and military installations can significantly exceed civilian limits under certain events/conditions. What started out as, for example, a 400V/m susceptibility specification might end up at 3200V/m — or even higher — design margin level for one’s equipment in order to have a safe design.

Often broad-band digital signals are the same way — there is a very low energy per bit, and multiple RF sources can combine to cause small noise events that disrupt individual bits. This is very different than most susceptibility specifications and tests, which test one interference channel at a time. Here again, often much margin is required or bit errors will start to significantly degrade throughput at some possible point in the future. Other means of dealing with the interference may be required, including ECC/EDAC in the protocols, or budgeting plenty of bandwidth for redundancy, as well as having redundant links. Sometimes one may think that it's possible to just ride out a few errors. One may discover later that with other data traveling the same link, a redesign is called for; it's best to anticipate these problems.

As one can see we, as engineers, need to think through the unobvious aspects of a specification, often to better determine the true requirements. Have you ever encountered a case where in order to have a safe design, one must exceed a specification from a customer by a very large margin to have a safe design?

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16 comments on “Design Margins in Analog & Digital

  1. eafpres
    April 19, 2013

    Hi William–interesting example regarding RF exposure.  Got me to thinking about ESD.  Testing usually involves one strike at a time from an ESD source.  Do you have any examples of additive effects in ESD events that could exceed margin?

  2. BillWM
    April 19, 2013

    I know sometimes even though the 8KV limit seems like it will be OK, 15KV is specified for a test limit for ESD.  And that some companies repeat the # of discharges a number of times for margin in that respect.

  3. jkvasan
    April 23, 2013


    Very informative post.

    For a medical equipment we tested it upto +-8KV. The repeat discharge was done 10 times in a row for each point and each level.

    I hear telecommunication equipment is expected to be tested around 15 KV, is it true?

  4. amrutah
    April 23, 2013

    William,  Thanks for the psot.

           As you mentioned, the design margin is what we survive on. Everyone has margin from the system to design to component and tighter we are within the spec the more we are safe when the random mismatches that arise due to the statistical behaviour of the components is consider, but the problem is we over design the module. Example: The tighter the noise figure  in the speaker path or the handsfree path will help, but we will end up burning more current (though within the spec).

  5. BillWM
    April 23, 2013

    One can get a lot of “experience” about a product pretty fast with regard to issues by reading old accident reports, court cases, and product history files — still one needs judgment and a good measure of practical experience —

  6. Davidled
    April 24, 2013

    It sound like more experience engineer gets better specification of design. But, implementing specification has always hole (imperfect), because of the limitation of technology and/or cost of product in some case. Tracking defect product may be a different aspect. The detailed specification is an acceptable. But designing the system by specification is totally a different story.

  7. Davidled
    April 24, 2013

     I got GPS antenna module. There are some parameters for each frequency band. There is no ESD information. Should 15KV be applied to GSP module?

  8. Hughston
    April 29, 2013

    Normally with ESD you test from the lower voltage ranges to the higher ranges. An antenna should have a high insulation resistance and it should not break down at any voltage, but you can couple into the receiver and cause damage. The antenna protection used to be done with passive componets but protection diodes are very low capacitance now, so maybe that's a better way to go these days.

    Lower test voltages have faster rise times and can cause problems not see at higher voltages. That's why you test over the range of ESD voltages. You have a contact and non contact range of voltages. The type of artificial finger affects the test and normally I used the blunt type. Humidity affects the test results and the results are worse with low humidity. Testing in a humid environment is like cheating. Results vary widely with the type of test gun, so use a popular type and pay attention to the return strap of the test gun. You want low inductance on the return ground to get a faster rise time on the pulse.

    The best ways to protect against ESD are to 1) have high insulation resistance or large air gaps, 2) design well for EMI, 3) have a good series or shunt protection, 4) use parts with some transient immunity (meaning higher voltage breakdown or internal protection), 5) bury traces near edges where ESD can strike, 6)have a good path to ground for the transient.

    What is a good path to ground? The first choice is chassis ground or the input power source capacitor. A second choice might just be away from your sensitive IC. Another possibility is an ESD protection trace around the circuit card, but the ESD current can still jump across the card or induce current elsewhere. ESD likes pointy things and wants to jump there. It's like a lighting rod effect.

    Do a lot more testing once you think you have a solution. ESD testing test results can vary from day to day because of the humidity and it is hard to tell when you have a solution.


  9. Brad Albing
    April 29, 2013

    Good info. Especially about testing in higher humidity. I guess if you knew your equipment might fail, but you wanted to pass your official agency tests, you could test with higher humidity. If you want to know that your customer won't blow something up and get all cranky on you when they return the equipment, then you should test during low humidity.

  10. Brad Albing
    April 29, 2013

    Probably a business decision regarding testing more severely. May not psss the test, but that points to the need for an improved design. Or you can lower your standards, pass the test, ship the product – and deal with the consequences later.

  11. Hughston
    May 2, 2013

    Here is something to try with an antenna. Zap a grounded metal plate in the horizontal and vertical planes positioned nearby. The idea is to induce a transient into your product. It also makes a difference if your product is plugged in. If a product is plugged in, then that gives a higher current path for any currents. Even if you have a power source with high insulation, ESD will eventually blow right through it and you will start to notice. Unconnected battery powered products pass ESD relatively easily.

  12. Hughston
    May 2, 2013

    I don't think you will have additive discharge events with ESD because you are charged and then you discharge. But you can only partially discharge at higher voltage, then discharge the rest as you come closer.

    You do get cumulative damage to parts with more ESD zaps. One of the hardest aspects of ESD testing, is damage assesment. Your product may just start to reset more often. That reminds me of another important aspect of ESD design, Smart layout of your reset to prevent reset during zaps. However, some companies don't consider product reset to be an ESD failure.

  13. eafpres
    May 2, 2013

    Hi Hughston–Thanks for the comments regarding my earlier question on cumulative effects.  Your thoughts on cumulative damage make a lot of sense.  Do you think that is the reason test protocols ask for multiple zaps, or is it becuase the exact position and current path varies from zap to zap so it is a crude statistical attempt to “fully test”?

    I wanted to go back to the antenna topic.  Antennas are intentional radiators, and for things like FM can just be a piece of wire.  Therefore, there is a direct path of ESD to the front end of the radio.  The system designer should take care of this; it may not be possible to do so in the antenna design.

    Once with a large consumer electronics company we designed an antenna that had a hard plastic molded “sheath” covering a rolled-up flexible printed circuit inside.  The housing was ultrasonically welded together.  During ESD testing they found that a zap right on the weld line would impact the system and demanded we “fix” it.  We cried foul–they had not put any isolation (like diodes or, more commonly for antennas, isolation caps) in the design, and they didn't want to do a board spin.  We spent a couple weeks tweaking the weld setup until it just passed.  I think later they fixed the board design.

    Your point about creating enough of an external field to couple in is just as valid.  The solution isn't in the antnena, it is in the front end design.

  14. Hughston
    May 2, 2013

    I do not do radio front ends, but the radio products I worked on used the inductor of the matching network as front end protection. Two other possibilities are some of these very low capacitance protection devices and an air gap discharge protection. Either of the second two choices might give you capacitance problems. When I was thinking of antennas, I was thinking of the insulated type or internal antennas. Both are isolated, but they can receive an induced transient.

    The standard test procedures call for multiple zaps because you often have a lot of entry points for ESD. You want to find them all. And you want to get enough zaps to get that cumulative damage effect. A good design does not let the ESD gun discharge at any voltage. With good isolation you are getting a free pass when you can't discharge.

    Your discussion of the current path brings up another test method. Remove the housing if you can and turn off the lights. You should see the ESD going to the same place every time when you hit in the same spot. The PCB might even get burned black. That should get you thinking about burying traces on the board for isolation and giving physical separation between discharge points and your susceptible parts. You might even solder a wire with a loop on the end to that spot, and zap away repeatedly.

  15. yalanand
    November 30, 2013

    @DaeJ, I think you can not apply 15 Kv to GPS module because this may destroy the  gate oxide of CMOS transistors inside the GPS module ,if it is damaged once the IC will be useless. So we have to be careful about applying voltages.

  16. BillWM
    November 30, 2013

    @Yanland — Antennas often use shorted quarter-wave stubs to shunt ESD to ground while allowing RF to pass —  look them up on GOOGLE –

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