ABOUT THE AUTHOR
Andrea Gerosa received a M.S. and a Ph.D. in Electronic Engineering
from University of Padova, where he currently holds a research assistant position. His research interests are focused on the design of CMOS analog IC. Particularly he has dealt with the design of acquisition systems for very fast applications and slow but low noise systems. In that context he has designed SC and Log-domain filters and sigma-delta or pipeline ADCs. Gerosa is author of more than 10 papers in international journals or conferences and is a member of IEEE. |
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Considering the design of any Switched
Capacitor (SC) stage, the operational transconductance amplifier
(OTA) is surely the most important and elaborate circuit block. As a consequence, an efficiently designed OTA can
make the difference between a high or low performance SC filter.
Depending on the particular application, the optimized figures of
merit may vary. Nevertheless, reducing power consumption is always
important.
An effective approach to minimize power consumption is highly
desirable during the design phase of the OTA. In order to achieve
this goal, it is necessary to have some basic formula describing
the OTA's behavior and the main trade-offs in OTA design.
Documentation describing the analysis of different OTA
architectures has been around for a long time. However when a designer tries to exploit these
results during the synthesis of an OTA, he may face the problem of
managing a set of equations with many degrees of freedom. If this
problem is addressed properly, the result is an almost optimized
OTA, even though the equations are quite simplified. If not
addressed correctly, the OTA could perform poorly.
This work proposes a possible procedure to exploit all the
information carried out by the basic OTA equation in order to
design a power-optimized OTA. The proposed procedure will refer to
an OTA intended for a SC integrator stage, which is often the core
block of many general SC filters. Furthermore we will assume that constraints in
terms of accuracy and sampling frequency (in other words, settling
time of the stage) are given from a system-level design. The
accuracy requirement also limits the dynamic range (DR) of the
stage. This parameter basically depends on the OTA output voltage
swing and on the integrator noise. The voltage swing is set in the
proposed procedure, considering the power supply value, while the
OTA noise contribution is minimized. In SC filters, the main noise
contributors are the switches and that the total noise power is
basically inversely proportional to the integrating capacitor. Therefore it is quite reasonable just to minimize
the OTA noise, without posing a strict constraint. Conversely, you
must consider the noise from switches more carefully and set the
integrator capacitors in order to ensure an acceptable noise level.
Since the noise analysis in SC networks goes beyond the scope of
this article, we will assume in the OTA design that capacitor size
is properly set during a system-level evaluation of noise.
The SC network used in this paper is the typical non-inverting
integrator (Figure 1 ) where C_{P} and Vd represent
the parasitic capacitor and the voltage at the OTA input,
respectively. This paper refers to a single-ended circuit for
drawing clarity, but you can apply all of the equations to a fully
differential circuit.
Figure 1: Â The circuit schematic of the
non-inverting SC integrator.
In order to evaluate the settling time of the stage, use the
following parameters:
Assume that during phase b , capacitor
C_{S} is precharged to V_{step} . When phase a begins, the voltage Vd becomes
Referring to the circuit schematic of a folded cascode
(Figure 2 ), we observe that if Vd is larger than the
saturation voltage of the input pair V_{d1} ^{SAT} ,
the OTA enters in the slew rate regime. As a consequence, its
output voltage becomes a linear function of time, with a slope
equal to the slew rate (SR), defined as
where I_{B} is the bias current of the input pair,
g_{m1} is its transconductance, w _{u} is the OTA unity gain frequency,
and C'_{L} is the total output load capacitance, accounting
for the C_{L} in Figure 1 and for the parasitic
capacitance of the output stage and feedback network.
Figure 2: Â The circuit schematic of a folded cascode
OTA
Assuming that the OTA exits from the slew rate regime at time
t_{SR} , the variation of the output voltage during the
slewing behavior is D V_{out} =
SRÂ·t_{SR} . Correspondingly, the variation of Vd is
Equation 4 implies that
The slewing phase ends when Vd equals
V_{d1} ^{SAT} , therefore Vd(t_{SR} )=
V_{d1} ^{SAT} and from Equation 5 it
descends
Once the slewing phase is ended, the OTA shows a purely
exponential settling, where the dominant pole is w _{p} = f_{FB} w _{u} . As a consequence, the total
settling time is
where e is the required accuracy for
the SC stage.
The remaining design constraints are related to the output
stageÂ—you must design the output transistors to exhibit a
saturation voltage, which allows it to keep all the devices
saturated within the full output voltage swing. Moreover, the
parallel of the two cascodes' output resistance is the effective
output resistance R_{OUT} of the OTA and is directly
related to the DC gain of the amplifier (Av_{0} ) as
Finally the input-referred noise of the OTA is expressed as
Therefore, if the saturation voltage of M3 and M9 are maximized,
the extra noise contribution of these devices is minimized.
You can use the equations presented in the previous section that
completely describe the OTA behavior to design an amplifier. The
main goal in the proposed approach is to minimize the power
consumption, hence you must minimize the bias current. The bias
current of the input differential pair is primarily related to the
stage settling timeÂ—the larger is the current, the higher
frequency is w _{u} , in other
words, w _{p} , leading to a
shorter settling time. From another point of view, you can make
w _{u} larger increasing
g_{m1} by means of making the transistors bigger; however
this does not necessarily imply a faster OTA. In fact, the
parasitic capacitance C_{P} is also increased, therefore
f_{FB} becomes smaller and w _{p} is pushed towards lower
frequencies. Therefore a tradeoff between the increase of
g_{m1} and C_{P} exists. This is confirmed by
Figure 3 where curves corresponding to constant settling
time are plotted in the W_{1} -I_{B} plane. You can
single out an optimum couple W_{1} -I_{B} for every
settling time.
Figure 3: Â A contour plot of ts as a function of
W_{1} and I_{B}
The Design of a Folded-Cascode OTA
The proposed design procedure is based on the tradeoff described
in the previous section. Starting from the requirement in terms of
settling time, you can single out the best value for the bias
current and the input transistors. The parameters included in
Equation 7 are all known from the system-level requirements,
except for the contribution to the load capacitor of the output
stage. You can estimate and then double-check this capacitance once
you design the complete OTA. If the real parasitic capacitance
results are much different, you can easily iterate the procedure
with a more realistic estimate.
Once you design the input stage, the output stage transistor is
sized making the sum of the saturation voltages fit into the
voltage headroom allowed by the output swing. The saturation
voltage of transistors M3-M9 is made bigger than the voltage of
M5-M7; as a result, the noise contribution is minimized according
to Equation 9 . Such a design choice enhances g_{m5}
and g_{m7} , boosting the output resistance of the two
cascodes and hence R_{OUT} . Consequently, the requirement
in terms of DC gain is more easily satisfied.
A folded cascode (Figure 2 ) is designed in 0.8Âµm
CMOS technology, using the proposed procedure. The obtained transistor sizes and main parameters
are summarized in Table 1 , where it is apparent that the
performances estimated by the equations and extracted from
simulations are quite similar.
Calculation | Simulation | |
Unity Gain Freq. | 197 MHz | 210 MHz |
Settling Time | 18.2 ns | 18.6 ns |
DC Gain | 61.1 dB | 63 dB |
Phase Margin | 64Â° | 60Â° |
Output Swing | 2.07 V_{PP} | 2.05 V_{PP} |
Table 1: Â The main parameters of the designed
OTA
Extension of the Procedure to Other Architectures
You can easily extend the proposed procedure to other OTA
architectures, for instance a two-stage design. Since you need to
frequency-compensate this OTA, for example using a standard Miller
compensation, you modify the expression for the unity gain
frequency w _{u} as
where C_{C} represents the compensation capacitor. Since C_{C} is a new variable in the
equation set, you must also consider an additional equation. This
comes from constraint on the phase margin, which equals
where g_{mOUT} refers to the active transistor of the
second stage. Introducing Equations 10 and 11 in the
procedure, you can perform the design similar to the case of the
folded cascode OTA.
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