Our guest author is Matthew Hann, SAR ADC Product Line Manager, Texas Instruments.
One of the most challenging aspects in optimizing the performance of a successive-approximation-register analog-to-digital converter (SAR ADC) is the design of the anti-aliasing filter (AAF). This simple, yet highly significant single-pole filter can cause a lot of headaches if not properly balanced with other variables. These variables include input driver bandwidth and stability, the input capacitance of the ADC, the system settling requirements, and overall system accuracy targets.
Figure 1 shows a typical SAR ADC data acquisition block diagram with a simplified amplifier and sampling circuit internal to a SAR ADC. The ADC’s sampling capacitor (CSH ) is connected to the input through the sampling switch during the sampling phase and remains isolated during the conversion phase.
The AAF in the SAR ADC has two distinct purposes in a precision signal chain:
- Noise filtering: removes extrinsic, wide-band noise and aliased harmonics generated by the signal source and the intrinsic noise of the driver amplifier and signal chain.
- Charge reservoir: provides an instantaneous charge at the start of each sampling phase, to the sampling capacitor (CSH ) to charge it up to the level of the input voltage. This charge demand creates transient distortion at the amplifier output, which can be mitigated through the use of the AAF capacitor (CFLT ).
Thus, the role of the AAF at the input of a SAR ADC is absolutely critical in achieving performance. However, this simple single RC combination can be challenging. Achieving performance requires a delicate balance in filtering, effective number of bits (ENOB), and settling.
Here are three rules of thumb that can provide a good starting point for optimizing the AAF:
1. Noise filtering to achieve required system ENOB
The AAF is a single-pole filter that assumes a corrected brick wall estimation of the cutoff frequency for the AAF (fFILTER ). Thus the post-filtered RMS noise of the input driver amplifier (eN_AMP ) can be estimated using the total RMS noise (eN ) to give the following calculation:
To meet ADC ENOB specifications, ADC (eN_ADC ) noise must be dominant. If eN_ADC is at least three times greater than eN_AMP , then by vector addition eN_ADC dominates the total noise, eN_TOTAL :
2. Minimizing harmonic distortion due to settling errors
For a high-resolution SAR ADC, one of the best ways to measure settling of a sine wave input is to measure the ADC’s overall performance. Two ADC parameters most affected as a result of improper settling are linearity (under dc test conditions) and distortion (under ac conditions).
The settling error at the ADC’s input is worst if the input signal changes drastically between any two ADC conversion cycles. For sinusoid inputs, it is assumed that the maximum settling error occurs at the maximum rate of change (see ΔVMAX in Figure 2 ). On the contrary, at the sinusoid input peaks, when the input rate of change is low, the settling error can be assumed to be minimal.
Using the derivation for settling peak error, total harmonic distortion (THD), and the ADC conversion time (tCONV ) (see Three 12-Bit Data Acquisition Reference Designs Optimized for Low Power and Ultra-Small Form Factor (TIPD168), Texas Instruments), a transcendental equation for RFLT and CFLT is established:
Furthermore, the voltage droop on CFLT can be minimized by assuming that more than 95% of the charge will be provided by CFLT . The remaining 5% will be replenished by the driver amplifier between ADC conversions. Therefore, equation 4 can be used to set the minimum value of CFLT :
Also, CFLT impedance at the frequency of interest (fIN ) should be at least 1 kΩ to avoid degrading operational amplifier performance that is typically characterized for 1 kΩ or larger loads. Since capacitance impedance is inversely proportional to capacitance, CFLT maximum can be established from 1 kΩ minimum.
3. Driver amplifier stability
If the open loop amplifier output impedance (ZO (ω)) is too large, amplifier stability can degrade with the interaction of CFLT and RFLT . Note that ZO (ω) can be commonly found in amplifier typical impedance plots as the maximum impedance at high frequencies. Generally, it is possible to have good stability as long as RFLT dominates over the amplifier’s ZO , making RFLT the impedance that interacts with CFLT . As a good rule of thumb, the amplifier’s ZO should be at most nine times RFLT . Also, this can determine RFLT maximum.
Please join us next time when we will discuss noise figure (NF) basics.
Special thanks to Rafael Ordonez, SAR ADC Applications Engineer at Texas Instruments, for his insights and expertise on this topic.