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Developing an Ultra High Intercept Last Gain Stage to a 14-Bit High SFDR ADC (Part 2 of 2)

While ADC’s have continued to improve in their IM3 characteristic, net system performance can sometimes be limited by the last gain and filter stage into the ADC. Recent amplifier advances have opened a path to very low power solutions retaining the full ADC capability. Part 1 showed an example design that seemed to provide a viable 19dB gain solution with a very nice interstage bandpass filter to control noise and out of band HD terms.

In part 2 here, the SNR and HD performance of the single tone 70MHz FFT is significantly improved by adding small series resistor at the ADC input pins. From there, a successful source signal set up for  < -115dBc IM3 testing is shown and 2-tone 70Mhz FFT results taken showing improved performance over the data sheet ADC only data.

Michael Steffes is Sr. Applications Manager/High Speed Signal Path Products and Jian Wang is Lead Applications Engineer/ High Speed Signal Path Products at Intersil Corp.

Read full article here.

Read part 1 article here.

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