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DFT—The Easier Way to Test Analog ICs

These days, due to the ever increasing complexity of devices and the demand for better product quality, it is vital that ICs are tested as quickly and as efficiently as possible. Test engineers are advancing on several fronts in an effort to ensure the testability of ICs and other complex semiconductor devices. The test engineer's goals include shorter design cycles and lower defect levels at lower costs of test. Their offerings are putting constant pressure on development of new and stable design-for-test techniques (DFT). This article mainly describes the view to analog IC testing, which in particular focuses on a switch mode DC/DC converter.

In the past, test engineers used an operational test to verify the functionality of such devices, yielding a number of disadvantages:

  • The quality of the device may not be guaranteed, which in turn could yield a higher rate of field returns. In other words, the device initially passes the operational test, but certain structural blocks may not be functioning correctly and, due to the nature of the operational test, are overlooked. Accordingly, faulty structural blocks are only noticed in field application.
  • Operational tests present parasitics, caused by stray capacitances and inductances, cross-talk and long traces, as well as high currents present in an operational test, make testing the device at wafer probe extremely difficult, if not impossible.
  • Many functions are individually not available for testing in full operational mode. Such functions include RDSON measurements of power transistors in switch mode converters.
  • An operational test may not facilitate diagnostics for the failing device. Accordingly, no evidence is available for the test engineer on where, how and why the device has failed. This lack of information complicates and prolongs the debugging process for the design engineer during device evaluation.

Due to the increase in DFT development and research, test engineers can now dynamically access each individual, structural block of an IC, with device specific testmodes. The purpose of using this technique is to ensure that an IC operates correctly in the designated application after it has been manufactured and that the good, functional ICs are separated from the faulty ones.

Using testmode development may result in the following advantages:

  • Improved product quality
  • Shortened time to market
  • Higher test coverage and therefore fewer test escapes
  • Reduced test time
  • Reduced test costs.

Together with the designer, the test engineer can discuss possibilities on how to easily test individual functional blocks. Based on the datasheet, a test plan is drawn up, where each device block is described along with the method for testing it. From this it becomes obvious that many of the device functions are not accessible/testable through an operational test.

It is then up to the designer to introduce internal hardware that facilitates easy test, easy access to complex blocks, and allows the test engineer to comfortably switch between structural blocks for test. This can be done in a number of ways.

Test Mode Detection

Further to the normal operation of the device, additional circuitry is implemented to cover the DFT functionality. This circuitry only becomes apparent once the device has been entered into its respective test mode. In other words, the test mode is only active for a short period of time during probe and final test where a functional block needs to be tested. During normal operational mode, the DFT circuitry remains dormant. A compromise then has to be found between either a high-test coverage with the disadvantage of a greater silicon chip area or lower test coverage and smaller chip size.

There are multiple techniques known to test engineers that make test mode entry possible. Access to a specific test mode should be simple and user-friendly, but should not interfere with the normal, operational functionality of the device. In other words, during operating conditions, the device is prohibited to enter the test mode.

The selection of the test mode entry method depends on the device pin count, device complexity and the number of implemented test modes in the device. Different methods by which it is possible to enter a test mode include:

  • Serial/parallel communication interface
  • Exclusive pins for test mode
  • Multi-level voltage sequence
  • Reassignment of device pins in test mode.

Although there are more methods to enter test mode, JTAG (Joint Test Action Group) interface is commonly used for testing digital devices. This article explores these four methods in detail.

Serial/Parallel Communication Interface
Many devices use internal interfaces (I²C, RS232) to control or communicate with other external hardware. This interface can be developed so that the device can also enter test mode as an option. No additional device pins are required to drive the device into test mode. As shown in Figure 1 , an I²C interface is used to receive data from an external source and concurrently send the data to specific registers (R1, R2, R3) of the device in operational mode. The test mode can be activated by configuring the device so that when a specific pattern is written to a register, it will change its properties and become solely available for test mode usage. An extra register R4 (as shown by the dotted line) can also be implemented for the exclusive use of test mode entry.


Figure 1:  I²C interface control

Exclusive Pins for Test Mode
A common and uncomplicated approach is to have an additional bond pad/pin available for the exclusive use of test mode entry. If the bond pads are only accessible at probe test, the device can only enter test mode at probe test. These bond pads are not bonded during assembly and therefore not accessible on the final packaged unit. No precaution is necessary to protect this device pin against mishandling and Electrostatic Discharge. This implies a deep test-coverage at probe test, followed by appropriate coverage at final test with the packaged device.

Multi-Level Voltage Sequence
A very common method is to give a designated pin multi voltage-level capability. Figure 2 shows the principle circuitry for a dual test mode (TM1 ,TM2) device.


Figure 2:  Multi voltage-level test mode detection

TM1 Activation
Raising a designated pin voltage (in other words, Pin A) above the highest occurring voltage (VDD – Supply voltage), forces the device into test mode TM1. The needed Voltage Threshold (VT) to exceed the supply voltage (VDD) for proper test mode entry is determined by the process technology in which the device is fabricated, and the voltage threshold (VT) is typically in the range of 0.5 to 1.0V. The voltage applied to the Pin A must be stable to maintain test mode operation. For a given VDD of 3V the voltage at the Pin A must be raised to 3.5V; 4.0V for test mode entry. After entering test mode, operational usage of the Pin A is prohibited. Decreasing the Pin A voltage by one VT down to VDD level (3V), causes the device to drop out of test mode and return to operational mode again.

If the functional usage of the Pin A is needed in test mode for testing as well, the activation of test mode TM1 can be latched using a simple Flip-Flop illustrated with the dotted line in Figure 2 . Once test mode TM1 has been activated and latched, the stable pin A voltage is no longer required to maintain test mode TM1 as long as Pin A voltage is less than VDD plus VT. The Pin A is then available for test purpose as well. Exiting TM1 is performed by resetting the latch. This occurs by decreasing pin A voltage down to VDD level and increasing it again to VDD plus one VT.

TM2 Activation
An implemented second test mode (TM2) can be activated by raising the pin A voltage higher than the TM1 voltage level by one VT (Figure 2 ). For instance, the applied Pin A voltage is 3.5 to 4.0V and the device has entered test mode TM1. Raising the Pin A voltage threshold by another 0.5 to 1.0V causes the device to leave TM1 and enter TM2. This voltage threshold must be stable to keep the device in test mode TM2. An interlock allows only one test mode TM1 or TM2 to be selected at a time.

Reassignment of Device Pins in Test Mode

Implementing multiple test modes (number of test modes > 2) requires a test mode select mechanism that differs from the above dual test mode detection (Figure 2 ). After entering the test mode, a pin is assigned as input for clock pulses. The number of applied clock pulses—detected with the rising edge—determines the selected test mode (TMx). The clock counter length and the complexity of the test mode decoder (Figure 3 ) determine the number of implemented test modes.


Figure 3:  Test mode decoder

Each implemented test mode (TMx) facilitates the test of an internal block (BLOCK1 -> BLOCKm, Figure 4 ) of which neither input and/or output pin(s) are directly accessible or testable in normal operational mode. For instance, the output stage of BLOCK1 is input for the subsequent BLOCK2. However, BLOCK1 is not apparent on a device pin. Test mode ensures that internal nodes are multiplexed to externally accessible pin(s). By way of example, test mode TM1 and the MUX make the output node of Block1 apparent on external designated device Pin B.


Figure 4:  Test modes facilitate the test of an internal block

Implementation in a Switch Mode DC/DC Converter

The real functionality of the DFT option is explained on a switch mode DC/DC converter that implements mainly analog but also digital functions. Implementing a test mode detect sequence combined with a clock-driven test mode decoder, the device uses a static multilevel signal on a LBI pin (Low Battery Input) to detect test mode, combined with reassigned clock functionality on the EN pin for specific test mode decoding (TMx).

The voltage level (VIN plus one VT) applied to the LBI pin enables the test mode decoder. Test mode entry voltage must be stable to keep the device in test mode. (test mode detection in Figure 2 ). Concurrently with the applied voltage level (VIN plus one VT) the test mode decoder is enabled. This can be triggered at any time by clock pulses on the EN pin to enter the required test mode. To set the device into test mode 2 (TM2, Test Mode Decoder in Figure 3 ), it is necessary to apply two clock pulses to the EN pin (Figure 5 ).


Figure 5:  Two clock pulses applies to the EN pin

The actual device, a switch mode DC/DC converter, uses the methods mentioned above for test mode detection and test mode decoding. Figure 6 shows us the total test coverage of a switch mode DC/DC converter by using test modes.


Figure 6:  Block diagram of switch mode DC/DC converter

On the current device only digital signal appear as output of the internally tested block and are multiplexed to a common output pin (LBO – Low Battery Output). Access to all the inputs of the internal blocks is available using device pins that have identical functionality in normal mode as well as in test mode. While continuously monitoring the LBO pin, it is for example possible to ramp a voltage up and down on the SENSE pin (Figure 7 ) thereby gaining an accurate and important threshold of an internal comparator that complies with a key parameter in the datasheet.


Figure 7:  Voltage ramp

Conclusion

High-quality test is a critical part of IC manufacturing and is necessary to avoid shipping defective parts to customers. Acceptable test approaches of the past are no longer effective in many ways due to the increase in device complexity, the demand of faster cycle times, and total test coverage. Therefore, more sophisticated DFT techniques are being utilized in IC testing. This allows engineers to dynamically test semiconductor devices, thereby providing customers with products of the highest quality.

Reference
Dr.Christian V. Schimpfle and Joerg Kirchner

“A Step-Down Conversion Concept for PWM-mode Boost Converter”

About the Authors
John Constantopoulos is a product/test engineer for Portable Power Management at Texas Instrument in Freising, Germany. He holds an electronic engineering degree (Dipl. Eng) from the Technikon of Pretoria, and can be reached by email at .

Walter Nadler is a product/test engineer for Portable Power Management devices at Texas Instruments in Freising, Germany. Prior to the power management department, he worked as a product engineer for TI's RFID transponder devices. He holds a degree (Dipl. Eng. FH) in electronic engineering from the Fachhochschule Furtwangen, and can be reached by email at .

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