I was out to dinner in Montreal a few weeks ago. As I walked down the four flights of dark, narrow stairs from the restaurant to the street, I stumbled on the last step and fell on my hands and knees. Ouch. To try and save face, I explained to my dinner hosts that, just about every time I travel outside America, I manage to trip with my feet at least once. Later it struck me why this always happens.
One problem with living in America is that our litigious society has forced rigorous conformity in simple things such as the height of a stair step. This uniformity subconsciously trains people to go about their business mindlessly without worrying about things as basic as watching your step. Some might think this is a good thing, and it might be in the case of staircases. But subconscious dumbing down can also instill unnecessary fears as one's mind reconnects to what was once a very basic process.
Take analog IC engineering. For the past 40 years, most analog ICs have been designed with some form of SPICE simulator. Originally, any engineer who used SPICE knew the value of the parameters GMIN, RELTOL, ITL5, and ABSTOL and how they facilitated a simulation. An engineer could quickly write a text-based net list to simulate a small circuit. SPICE simulators with simple interfaces are still available today — many for free — but the ones that are not free (and cost five or six figures) have effectively mitigated the need to understand basic SPICE aspects. I call this a dumbing down of the design process.
Just like the slip-and-fall laws for staircases, dumbing down SPICE has resulted in fear by many that, unless one has access to expensive design tools to hold your hand, somehow the design won't work or will take much longer to complete. But this just isn't true for a large segment of analog IC engineering.
Despite what many might claim, SPICE hasn't changed since its introduction in the 1970s. Sure, there have been lots of improvements in simulation time and managing larger circuits, but Moore's Law has afforded those improvements. Both the MIPS rate and circuit memory capability have increased at least a millionfold since SPICE first showed up on a PC, while the improvement in SPICE algorithm speed has improved only 10-fold at best.
This dumbing down of the analog IC design process is not limited to SPICE. The same things are true for analog IC layout tools. For nearly 40 years, GDSII (pronounced GDS-two) has been the dominant format for layouts sent to the wafer foundry. It's is not much more than a listing of polygon coordinates. Today, even on the most expensive tools, analog IC layout designers still use a mouse to point at coordinates on a screen to draw a polygon.
The most valuable historical improvement in the analog IC design process over 40 years has been the introduction of multi-project-wafer (MPW) services by pure play foundries. This was the great equalizing event between the Davids and the Goliaths of the analog IC industry.
I can recall several analog IC success stories that are based on low-cost MPW access to silicon prototypes, but I can't recall one analog success story based on the availability of advanced, hand-holding design tools. If anything, expensive tools are standing in the way of advancing the art of integrated analog.
I've tried to be careful in this blog to address only the analog aspects of an IC design. If your requirements are heavily digital — more than a few thousand logic gates — then I certainly concede that digital IC design tools share equal footing with MPW services in terms of advancing the art in IC design. In fact, digital tools are advancing so fast that a modern digital engineer is no longer an electrical circuit engineer.
I also wouldn't have written this blog if advanced analog IC design tools were affordable for a small company or startup in the same way that software tools are for Internet and applications programming. But they aren't — and for very good reason. The size of the market is too small. But don't let that stop you.
If your requirements are for an essentially custom analog IC design with no more than a few thousand gates of logic, then there is very little reason not to set your fears aside and walk down the stairs like you learned when you were two years old. The big difference now is that evaluating your design doesn't require owning a fab. And the quality of the resultant product will be a byproduct of the engineer who runs the tools, as it has been for 40 years. I suppose that statement applies to digital engineering, as well.