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Review of GaN-on-Si RF Power Device Market

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Brad Albing
Brad Albing
5/28/2013 11:19:56 PM
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Re: good discussion
Yep - very interesting - and as you noted, drawing a good number of comments (14 as I write this) for a newbie blogger here.

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analoging
analoging
5/28/2013 7:50:22 PM
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good discussion
Interesting comments. Glad to see so much discussion. This appears to be one of the more active UBM tech blogs compared to the others in the network. Happy to see new ideas generated for other articles.

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analoging
analoging
5/28/2013 7:48:38 PM
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Re: wafer size
Most RF IC companies use much smaller wafer sizes than what is used in high-performance logic and memory devices. Typically RF or power ICs use 6 inch or less GaN, GaAs, or Si due to lower production volumes involved vs. logic and memory fabs. Equipment is often purchased as refurbished if given the choice. Foundries offer varying wafer sizes but are relatively larger in wafer size offerings due to more advantageous economies of scale. For Si, I believe most offer 8 inch or larger.

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analoging
analoging
5/28/2013 7:43:14 PM
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Re: Re : Review of GaN-on-Si RF Power Device Market
Yes, many techniques can be used to account for lattice mismatch. Buffer layers of intermediary alloy films similar to GaN or Si can be grown. In addition, companies can use wafer slicing and wafer bonding to avoid having to do heteroepitaxial growth of GaN on Si which lessens defect density in GaN layer. This is known as template layer transfer which Soitec has developed for GaN applications of this nature.

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amrutah
amrutah
5/28/2013 10:34:16 AM
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Re: GaN transistors and models
Yes, I agree with Brad.

Earlier this month there was a blog by Scott, very helpful.  The best would be to have information regarding different technologies, the modelling methodology and market presence (present and future).  This will help many and guide many.  May be a series of blogs.

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Brad Albing
Brad Albing
5/28/2013 9:26:36 AM
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Re: GaN transistors and models
>>Since it is not a widely used process, how are the models developed for the transistor...

Looks like we should explore this in another blog

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Brad Albing
Brad Albing
5/28/2013 9:21:24 AM
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Re: Device sizes
DaeJ - so with larger wafers, we can get more ICs per wafer - but we may just get more defective ICs per wafer. So just having larger wafers doesn't solve the problem.

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Brad Albing
Brad Albing
5/28/2013 9:17:03 AM
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Re: GaN-on-Si looks promising
Like amrutah said, I also am not very knowledgable when it comes to various technologies - so this is real good info to see online.

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SunitaT0
SunitaT0
5/28/2013 7:04:25 AM
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Re : Review of GaN-on-Si RF Power Device Market
@Brain, thanks for the post. GaN on silicon carbide (SiC) substrate have good crystal lattice matching while GaN on silicon wafers makes use of already developed automated IC production facility. Clearly there is the trade-off between performance and cost. Even then is there any way this crystal mismatch taken care in GaN-on-Si process?

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DaeJ
DaeJ
5/27/2013 3:24:40 PM
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Re: wafer size
Some of tool might be scrapped or retrofitted. I am sure the manufacturing cost is increased and a lot of attention is costly required for a high density chips. But company saves their capital down road. There is g450 consortium for semiconductor manufacturing community.

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