The move to scale down to 0.18μm was based on the following: Reduce the feature size in the front-end of a device. Reduce the back-end or interconnect. Add more interconnect layers. Doing so would greatly increase the density of digital circuitry and reduce the intrinsic gate switching delay.
With the smaller geometry, the supply voltage had to be decreased to prevent voltage breakdown. Unfortunately, this led to an increased gate-switching delay in digital circuitry and lower dynamic range in analog circuits. Process designers lowered FET gate threshold voltage to compensate for the switching delay problem. In the analog realm, scaling did not bring much area reduction. However, it did yield higher-speed transistors, which led to silicon implementation of RF circuitry and high-speed analog blocks such as ADCs and DACs.
The problems in going below 180nm or even 90nm CMOS for analog can include further reduction in supply voltages, design productivity, and signal integrity. If you ask a group of designers the question in the title of this blog, you will get many different answers and opinions. It depends upon what you are trying to achieve in a highly integrated design. Note that engineers still do take the simpler approach and use single op amps and discrete transistors in their designs. Just as Bob Pease always reminded us: “KISS.”1
It really comes down to what you need to achieve in a system design and whether a highly integrated IC fits in your architecture. Complex systems on a chip (SoC) with mixed-signal design, embedded high-performance analog, and sensitive RF front ends combined with digital circuitry have achieved such breakthroughs as base stations on a chip. Smaller is better here; but smaller is not always the best way to go for all designs.
Analog circuit design challenges in nanometer technology
One main effect, and on the surface seemingly an advantage, is reducing power-supply voltages by scaling to a smaller line size. Scaling will not necessarily bring large-area reductions in analog as it does in digital. The active area of analog transistors is determined by kT/C thermal noise or mismatch-induced offset constraints. Such constraints can impede dynamic range and accuracy, depending upon size.
See Equation 1 for the relationship2 between achievable speed, dynamic range and power. The term “technconst” is an arbitrary constant:
So with respect to thermal noise, the constant on the right side of the equation depends only upon temperature. In the case of mismatch, the amount of mismatch in the technology process used will determine the outcome. See Figure 1 for a plot of these relationships for a real technology process.
(Image courtesy reference 3)
So we see for Figure 1 that for untrimmed or uncalibrated circuits, the mismatch limit determines the minimum required power consumed for a particular speed and dynamic range spec. The red squares in the graph mark real ADC designs.
As the technology scales, transistor mismatch will improve slightly. So if a designer needs the higher speed gained by the scaled technology, he will have to accept the increased power penalty at the same dynamic range.
For a fixed speed and accuracy, power would decrease from improved matching were it not for the reduced power supply voltage that comes with the nanometer technology. Now input-signal range headroom is reduced, and this in turn affects thermal noise and offset by needing tighter constraints there.
Next, how is analog design productivity affected by technology scaling? Since analog design is still considered a “black art,” a great many analog designs are carefully done by expert analog designers who take into account the myriad variables that can affect a good-performing analog circuit. Hence the design time for the analog portion takes longer and is more likely to have errors than their digital counterpart, which has better simulation and auto-routing capability in most cases.
Better analog CAD tools are in great demand
Finally, signal integrity can suffer as technology scales. Analog and RF circuitry are very susceptible when on the same die as “noisy” digital circuitry. Crosstalk — either radiated or conducted — can wreak havoc on sensitive analog circuits. Digital switching transitions contain significant harmonic energy due to their fast transitions. These upper frequencies may propagate through the shared substrate.
I firmly believe that these are not insurmountable problems in the integration of analog as next-generation scaled technology progresses to smaller and smaller lithography nodes. I am excited about what is to come as we break through paradigms of the present and move into the promising future of integrated electronics.
Just remember that there are still so many areas where reduced technology nodes are needed for analog performance, power, and die footprint improvements. The Ft in transistors of 350 GHz and beyond are possible now. These will see use in such circuit functions as LNAs (low noise amplifiers) and ultra-high speed data converter designs (which will also require higher data rate interfaces, by the way).
As good examples, take a look at reference 4, below, to see a 4.5mW, 8-bit ADC at 750 Msps, which could only be done in a much lower technology node like 28 nm. Or reference 5, which shows a 6-bit, 28 Gsps DAC at 90nm. We can go further with good examples that need the sub-μm nodes such as the work that IMEC is doing with Renesas or the base station on a chip that Freescale has developed. (See: Integrated RF Analog, Multi-Standard, Software-Defined Radio Receivers.)
What are your experiences working with sub-180nm and sub-90nm devices? For the analog applications, how did you deal with the limited available voltage range?
- KISS stands for “keep it simple, stupid.” In some attributions, the last “s” has more vulgar equivalent. The acronym can sometimes be traced back to army drill instructors' guidance given to recruits being trained.
- Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits, P. Kinget & M. Steyaert; CICC, pp. 333-336, proceedings of the IEEE, May 1996
- Analog and digital circuit design in 65 nm CMOS: end of the road?, Georges Gielen & Wim Dehaene
- A 4.5-mW 8-b 750-MS/s 2-b/Step Asynchronous Subranged SAR ADC in 28-nm CMOS Technology, Yuan-Ching Lien
- A 28GS/s 6b Pseudo Segmented Current Steering DAC in 90nm CMOS, Thomas Alpert, Felix Lang, Damir Ferenci, Markus Grözing, Manfred Berroth