Dolphin Integration readies high-yield circuit design methodology

PARIS — EDA and IP company Dolphin Integration SA said it has defined a design methodology that is said to assess the design yield for any memory generator.

Dolphin Integration (Meylan, France) explained that design yield can only be guaranteed by a combination of worst-case corners simulation and mismatch simulation. The embedded Memory Provider, the company claimed, provides a two-step methodology to take into account the offset for the design and the validation of any memory generator, with the objective of achieving high design yield while maintaining optimized performances.

Dolphin Integration said its method enables a a posteriori verification of mismatch and an a priori implementation during memory design.

In parallel, Dolphin Integration announced it has developed an approach to the development of Virtual Components of Silicon IP, dubbed Application Hardware Modeling (AHM).

The AHM approach, the company specified, aims at optimizing any critical function performed jointly by parts of the system, comprising some Virtual Component within a SoC, its PCB with relevant discrete components, such as Quartz, PMIC, or MEMS, along with application software.

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