The role of the analog ic designer is morphing, as became apparent in discussions with designers and eda vendors for my recent article on analog layout automation.
In the article we discuss the move away from the somewhat arrogant-sounding ambition of complete analog synthesis (you enter a specification and out comes a working analog circuit) to the more digestible model of 'productivity enhancers' – tools that aim to take onboard monotonous aspects of analog circuit design and layout, allowing the user to focus on the more creative elements of the task.
How effectively analog ic tools automate these tasks is a whole other discussion. What's more interesting is the implication of the latest generation of tools on the nature of the analog ic engineer's job today. Note that I say 'engineer', as neither the precise labels of 'designer' or 'layout engineer' necessarily apply these days – these are roles that appear to be merging, as designers increasingly take on certain layout duties.
Automation has long been the main catalyst for change in working patterns among analog ic designers; integration, miniaturisation and the need to generate more devices per engineering hour are among the drivers. But contrary to folklore, it is analog ic engineers themselves who are eagerly embracing automation. After all I had heard, I was semi-surprised to hear TI's analog EDA manager Chris Collins admit: “I love tools unfortunately, EDA vendors are not able to provide a completely automated analog solution like there is in the digital space for routing.” Hence why I don't quite buy the analogy that the impact of EDA automation is a little like the industrial revolution. After all, mechanisation and standardisation bound the poor into monotonous, unsatisfying work at the end of the 19th Century: automation has the potential to 'free' engineers from so-called monotonous, non-creative tasks.
For example, DRC can be monotonous, as CSR's head of physical design Paul Egan related to me: “When I started twenty five years ago, DRC checks involved printing out a plot at 100 times the size of the chip and sitting with a ruler in hand, seeing if you could find shapes that were smaller than the recommended size – literally checking by eye. Following that, there was a huge step forward when very simple design rule checks were introduced that would just check width and space. However, the processing time for 20,000-transistor design could take easily 24 hours and you might only check between 20 and 30 rules. Nowadays, the tools allow a 20,000-transistor design running on a multicore processor to execute a couple of thousand design rules in 20 minutes to half an hour. But it's a function of there now being a couple of thousand rules to be checked.”
So what does automating this mean for analog ic layout engineers of the future? Says Egan: “I believe that the next generation of layout guys will probably spend as much time writing code to generate and constrain layout as they will actually drawing shapes, looking things up and running DRC. We are probably in the last throws of having people sitting drawing shapes, certainly in the smaller geometries. To stay current, people are going to have to learn new skills.”
Similarly, Dave Millman, VP marketing at Ciranova acknowledged: “Designers and layout functions will end up working differently in the future. If they want to meet soc design cycle, it's not going to slow down for analog. Design rules at advanced processes are so much more complex and getting worse. If they want to deliver to those products, they are going to have to work with automation.”
My concern is for some of the creativity that analog designers are well known for – it would be sad if this 'artistry' was lost. Analog ic engineers are often referred to as crafts people, in both the sense of the hand-crafted aspects of some design and layout functions, and in the aesthetic qualities of the end-result. Hence why I was heartened to hear Eric Filseth, Ciranova's ceo say that they recognised they need to “keep the designer involved in making the high level decisions about what needs to go where on-chip.”
It strikes me that analog engineers (and vendors) need to be perfectly clear about what should be automated and what shouldn't. The distinction between the goal of productivity enhancements and full analog automation is a delicate one and has numerous implications on the future of analog ic engineering.
Oh, and by the way, analog synthesis isn't yet quite forgotten. Cadence's Randolph Fish commented: “What we have been focusing on is making the placement or circuit optimisation faster, or enabling the routing to be done faster. We don't think that replacing their capabilities is the sweet spot right now.” The key information there, I think, is the 'right now'. What will be interesting to see is how EDA vendors such as Cadence balance further automation enhancements without stepping on the 'creative' toes of their customers.
What are your views? Is the creative/artistic element of the analog ic designer's role in danger of being lost to increased automation? Do you relish spending more time writing code to generate and constrain layout? What are the implications of automation on analog systems designers? Your thoughts on this would be welcomed.