Today's electronics systems require lower

voltages, higher currents, higher power density, and higher

efficiency than their predecessors needed. These demands

necessitate the use of paralleled power MOSFETs or large-die

MOSFETs. Having to use these high capacitance devices has given

some designers an uneasy feeling about which approach to

use.

The successful design of robust gate-drive circuitry for high

voltage, very high current MOSFETs is no different than the driver

circuitry designed for smaller devices. It depends on an

understanding of the drive requirements, a good model to predict

the results, careful attention to the physical layout of the driver

board, and the selection of the proper circuit topology.

Figure 1 represents a generic gate driver circuit where the

switching speed is controlled by the total gate impedance

(R_{G} ), the total source inductance (L_{S} ), the

load resistance, and the device's characteristics. Once the load is

defined and the power-switching device is selected, the fast

switching speed is achieved by minimizing the two remaining

parameters, R_{G} and L_{S} .

**Figure 1:** A generic gate driver circuit where the

switching speed is controlled by the total gate impedance

(R_{G} ), the total source inductance (L_{S} ), the

load resistance, and the device's characteristics.

Although this article discusses a single MOSFET device, the

equations can be extended to paralleled devices by adding together

the parameters of the paralleled combination and treating the

paralleled devices as a single lumped device.

**Turn-On Breaks Down into Three Intervals**

The resistive load turn-on waveforms of a power MOSFET (Figure

2) can be divided into three intervals. In the first interval, the

gate voltage rises to a value where the device just begins to

conduct. This interval is controlled by the device's input

capacitance and input impedance. The second interval is the time it

takes the drain voltage to reach its minimum and the drain current

to reach its maximum. The input impedance, gate-drain and

gate-source capacitances, source inductance, G_{M} of the

device, and load current, control this interval. This period is the

most complex and represents the turn-on power losses. The third

interval is the period it takes the gate voltage to complete its

rise to the gate drive supply voltage and is controlled by the

input impedance and the input capacitance.

**Figure 2:** The resistive load turn-on waveforms of a power

MOSFET

**Interval One (t _{0} t_{1} )**

This period begins with the transition of the input voltage

(V_{IN} ) from the low value of the gate drive voltage

(V_{GG} ) to the high value of the gate drive voltage

(V_{GG} ) and ends when the gate voltage reaches a value

where drain current begins to flow (V_{GS(ON)} ). For this

analysis, the V_{IN} transition is defined as a step

function that occurs in zero time. Because no drain current flows

during this period, the drain voltage remains at the supply voltage

(V_{DD} ).

The equivalent circuit for this period (shown in Figure 3) is a

simple RC network made up of the input impedance (R_{G} )

and the input capacitance (C_{ISS} ) and is the sum of the

driver impedance, the gate resistor, and the internal gate

impedance.

**Figure 3:** The equivalent circuit for Interval One

The time of the period and the waveform can be calculated from

the RC time constant formula:

**(1)**

Solving Equation 1 for t:

**(2)**

Where delta V_{GG} is the total voltage swing of

V_{IN} .

From Equation 2, the device in Figure 1 would have a first

interval of:

Where C_{ISS} is the typical value from the data sheet

and V_{GS(ON)} is from the transfer characteristic curve on

the data sheet.

**Interval Two (t _{1} t_{2} )**

This period begins when drain current starts to flow at the end

of interval one and ends when the drain current (I_{D} )

reaches its maximum value. A gate-voltage plateau marks this

period. The gate drain capacitance C_{GD} in conjunction

with the falling drain voltage, known as the Miller Effect, cause

this plateau.

Reading some papers on MOSFET gate-drive and switching

performance could lead you to believe that the rise time of the

drain current lasts for the same time as the gate voltage is

exhibiting the Miller Effect. The following analysis will show this

is untrue.

Using Kirchoff's Law, an approximate equation for the gate node

(when the rate of change of V_{GS} is much less than the

rate of change of V_{DS} ) is:

**(3)**

Solving Equation 3 for dt:

**(4)**

The change in gate voltage is related to the change in drain

voltage by:

**(5)**

Combining Equations 4 and 5:

**(6)**

Also:

**(7)**

And the drain current's rate of change is related to the drain

voltage's rate of change by:

**(8)**

Combining Equations 6, 7, and 8:

**(9)**

Solving Equation 9 for dt:

**(10)**

The solution of Equation 10 is not straightforward because

C_{GD} is voltage dependent and varies as a function of the

drain-source voltage and G_{M} is a function of the drain

current. An incremental solution for Equation 10 can be

accomplished using a spreadsheet and 25V incremental values for

dV_{DS} . An example of this technique can be found in the

downloadable spreadsheet.

**Interval Three (t _{2} t_{3} )**

This period begins when I_{D} reaches its maximum value

and ends when C_{ISS} is fully charged. Like the first

period, the equivalent circuit is an RC network made up of

R_{G} and C_{ISS} . The time of the period and the

waveform can again be calculated from the RC time constant formula

in Equation 2. However, the value for C_{ISS} is much

larger than in the first interval because the drain-source voltage

is much lower. This interval is not of major concern because all

activity with the drain voltage and current has been completed

before this interval starts.

**Turn-Off**

The resistive load turn-off waveforms of a power MOSFET (Figure

4) can also be divided into three intervals. The equations for

calculating the periods and waveforms are simply the reverse of the

turn-on where interval one corresponds to interval three, interval

two still corresponds to interval two, and interval three

corresponds to interval one.

**Figure 4:** The resistive load turn-off waveforms of a

power MOSFET

Figures 5 and 6 show actual switching waveforms from an

APT5O2OBN power MOSFET switching a 10.5ohm load at 250V with 51ohm

gate resistors. R_{D} is 4ohms and R_{1} is 3ohms.

The calculated switching waveforms are overlaid with dots. The

correlation between calculated and measured values is very good,

proving the validity of Equations 2 and 10.

**Figures 5 and 6:** Actual switching waveforms from an

APT5O2OBN power MOSFET

**Layout Considerations**

As demonstrated, switching a MOSFET on and off requires only a

simple circuit to charge and discharge the device's input

capacitance. However, this seemingly simple circuit is not without

problems and pitfalls. It is simple only when compared to bipolar

drives.

Problems most often encountered with the gate drive circuit

include:

- Voltage spikes large enough to rupture the gate oxide
- Oscillation
- Ringing or false turn-on.

Usually, these problems are the fault of the layout and not the

driver circuit's electrical design. To minimize these problems, the

following design rules and precautions should be followed when

designing and laying out driver circuits.

As illustrated in the previous section, the source inductance

plays a significant role in the switching speed by acting as a

negative feedback to the gate drive. Engineers cannot reduce the

source inductance in the device's package (L_{S} ), but the

inductance relating to the connecting circuitry (L_{C} ) can

be mitigated. Where the gate signal and the load current share the

same conduction paths (Figure 1) is the problem section. Therefore,

the load current should be diverted from the gate signal's path as

soon as possible — the closer to the source terminal of the

device the better.

Connecting the gate driver return to ground, instead of Point A

in Figure 1, adds the inductor L_{C} to the L_{S}

term of the switching speed (Equation 10) causing the switching

time to increase. Each additional inch of circuitry will add as

much as 20nH. Adding 20nH to the switching speed calculation

changes the results from a 20ns rise time to a 70ns rise time, a

350% increase.

A ground loop is an often-overlooked mistake in the gate driver

circuitry layout. A ground loop occurs when the gate driver

circuitry is tied to the power ground in more than one place,

resulting in load current flowing in the gate driver ground (Figure

7). This current not only results in slower switching speeds, but

also can cause excessive ringing on the gate, false triggering of

the power device, and oscillations.

**Figure 7:** Example of a ground loop

Minimizing the area of the gate driver circuitry loop, as Figure

8 shows, reduces the inductance in the loop and lowers the driver

impedance.

**Figure 8:** Minimized area of the gate driver circuitry

loop

A ground plane under the gate driver circuitry is helpful in

reducing noise injection into the drive circuitry. However, the

ground plane should be tied only to the power ground at Point A in

Figure 1. Great care should be taken not to create ground loops by

multiple tie points to the power ground. For a high side driver,

the ground plane should tie to the source of the high side device,

not to the power ground.

Do not intermix gate driver circuitry and high current carrying

load circuitry. Noise can be coupled into the gate driver circuitry

through stray capacitance or induced by radiated fields. The

results of the injected noise could cause excessive ringing on the

gate, false triggering of the power device, or oscillations.

The gate driver power supply should be bypassed with good

quality, high frequency capacitors because the power supply's

impedance is a part of the driver impedance (R_{G} ). The

capacitors should be connected as close as possible to the driver

to minimize the inductance.

**Gate Drivers**

To this point, the type of driver being used has not been

indicated; only that it represented 4ohms of the total gate drive

impedance (R_{G} ). Once the source inductance is under

control through proper layout, it is clear from the model in Figure

1 that the next way to improve switching speed is to reduce the

driver's resistance. Selection of the proper gate-driver circuit

topology accomplishes this task.

Gate drivers can be divided into two categories: discrete and

IC. In the past, discrete drivers have dominated, but IC types are

increasingly used because of their improved performance and lower

prices. I favor the IC driver over the discrete driver because it

uses fewer components, making the optimal layout easier to

achieve.

**Discrete Drivers**

Two types of discrete drivers are in common use: the

complimentary pair, bipolar NPN-PNP emitter-follower (Figure 9a)

and the complimentary pair MOSFET P-channel N-channel (Figure 9b).

Both types are referred to as totem poles.

**Figure 9:** (a) The complimentary pair, bipolar NPN-PNP

emitter-follower discrete driver.

(b) The complimentary pair MOSFET P-channel N-channel discrete

driver.

The bipolar totem pole is non-inverting and offers no voltage

gain to improve the pre-driver rise or fall times. It does provide

current gain to reduce the driver impedance to speed the charge and

discharge of the device capacitances. Once the input capacitances

are charged and the power device has been switched, the driver does

not require holding current. It offers medium speed and does not

perform well at higher conversion frequencies.

To facilitate higher frequency operation and faster switching,

the P- and N-channel complimentary pair MOSFET driver is used.

Unlike the bipolar design, the MOSFET totem pole is inverting and

offers voltage gain to improve on the pre-driver rise and fall

times. This driver suffers from shoot-through current caused by the

threshold voltage overlap during on and off transitions resulting

in increased drive power requirements. Because of the inverting

nature of the driver, it may cause false turn-on of the power

device during power up and power down, requiring under voltage

detection and hold-off circuitry.

**IC Drivers**

In the past, several companies introduced IC drivers with

reasonable performance and a relatively high cost. Recently these

and other companies have continued to improve the performance and

reduce the cost of the IC driver, making them more cost competitive

with the discrete driver. The IC driver is a better solution when

the fact it requires fewer total components is considered, making

it easier to meet layout design rules.

**Driver Comparison**

Table 1 shows a comparison between the two discrete drivers and

several IC drivers driving an APT5O2OBN device (0.2ohms, 28A, 500V)

switching a 10.5ohm load, 250V with no gate resistor RG. Shown in

the table, several of the IC drivers equal the MOSFET totem pole

and the remainder range between the MOSFET and bipolar totem pole

drivers.

**Table 1**

Driver |
Rise Time (ns) |
Fall Time (ns) |

MOS | 20 | 20 |

UC3710 | 20 | 20 |

M1C4451 | 20 | 20 |

M1C4429 | 30 | 30 |

UC3708 | 30 | 30 |

UC3711 | 30 | 40 |

Bipolar | 60 | 70 |

**Driving Large Die**

To this point we have been examining the APT5O2OBN, a relatively

large device. However, there are even larger devices in use such as

the APT5OM6OJN (0.06ohm, 71A, 500V). This device was switched with

a 3.5ohm load, 250V with 0, 1.5, and 3ohms gate resistor

R_{G} . The gate resistors were added to control excess

ringing caused by inductance in the load on the three faster

devices. The APT5OMGOJN is four times as large as the APT5O2OBN and

it would seem to present a much more difficult gate drive problem.

However, Table 2 shows that if the layout design rules are adhered

to as previously discussed, driving this device is not much more

difficult than driving the smaller device.

**Table 2**

Driver |
RG (ohm) |
Rise Time (ns) |
Fall Time (ns) |

MOS | 0 | 20 | 20 |

4451 | 0 | 20 | 20 |

3710 | 0 | 30 | 40 |

3711 | 0 | 40 | 50 |

4451 | 1.5 | 40 | 70 |

4451 | 3.0 | 60 | 100 |

The successful design of a MOSFET gate driver not only depends

on the selection of a low-impedance driver circuit topology but

also strongly depends on the layout of the circuit board containing

the driver circuit.

If a low-impedance driver circuit is employed and proper

attention is given to the layout, fast switching of large die

MOSFETs is not more difficult than driving smaller devices.

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