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Driving the reference input on a SAR ADC

Analog-to-digital converters (ADCs) perform conversions by comparing the input voltage level against the reference input; therefore, the accuracy, stability and noise of the reference directly affect the performance of the ADC.

In the classical successive approximation register (SAR) topology, the reference pin is the most sensitive, since this terminal presents a dynamic load to the reference drive circuit. In this article, I’ll provide an overview of SAR ADC reference input behavior and reference input drive circuit topologies.

Figure 1 shows a simplified schematic of a binary-weighted capacitor array on a SAR ADC.

Figure 1

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Binary-weighted capacitor array on a SAR ADC

Binary-weighted capacitor array on a SAR ADC

The SAR performs conversions in two phases: an acquisition phase and a conversion phase. During the acquisition phase, switch SA is closed, and switch SB and all other switches connect to VIN , where all capacitors acquire the input signal. During the conversion phase, switch SA opens and VIN disconnects from the internal capacitor array; switch SB connects to VREF . The SAR ADC operates by using a binary search algorithm to converge to the input signal. The binary-weighted capacitor array generates binary-weighted voltages as a function of the reference based on charge redistribution. The conversion algorithm starts with the most significant bit (MSB) and continues with each binary-weighted capacitor to the least significant bit (LSB), where a high-speed comparator performs the bit decisions.

The reference is sampled several times during the conversion phase for each of the binary-weighted bit decisions. Therefore, the reference input presents fast, high-current transients during the ADC’s conversion phase as each element of the binary-switched capacitor charges.

It is important to understand that the reference input current in the traditional SAR is not a constant, static current. Rather, the input current consists of fast transients as the binary-weighted bit decisions are made. Figure 2 shows the current transients on the reference input terminal for a classic 12-bit SAR ADC.

Figure 2

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SAR ADC reference input current and voltage transients during conversion.

SAR ADC reference input current and voltage transients during conversion.

The reference voltage must settle to the required ADC N-bit resolution at the end of each bit conversion clock cycle, or linearity errors and missing code errors may occur. Also, higher-resolution SARs will tend to have more demanding reference specifications because the reference input voltage must remain stable and settle to less than one LSB resolution. For example, a 12-bit ADC using a 5-V reference has an LSB weight of 1.22 mV. In contrast, a 16-bit device has a smaller bit-weight resolution of 76 μV, imposing a more stringent settling requirement.

In general, the reference driver circuit consists of a precision reference, an external reference buffer and a bypass capacitor. Figure 3 shows a typical reference input drive circuit.

Figure 3

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Typical SAR ADC reference input drive circuit.

Typical SAR ADC reference input drive circuit.

Most SAR ADCs require a large bypass capacitor at the reference input, typically in the range of 1 μF to 22 μF. The large bypass capacitor is required to replenish charge to the internal binary-weighted capacitor array, because each bit decision is settled in a few nanoseconds during each conversion clock cycle.

In general, series voltage references incorporate an internal buffer. However, in many cases, the reference may not have sufficient bandwidth or low output impedance over frequency to directly drive the ADC reference input and achieve good settling performance. External reference buffers are required in high-resolution applications when using fast sampling rates, as the reference input must remain settled within conversions.

The reference buffer is a wide-bandwidth amplifier that responds to the fast transient current requirements on the ADC’s reference input. A reference buffer must have low output impedance across frequency, and must be stable driving the large bypass capacitor. In addition, the buffer needs to have good DC performance, or low offset and low drift, to maintain the accuracy of the reference.

Many modern SAR ADCs incorporate internal references and internal reference buffers. Figure 4 shows a high-performance SAR ADC offering a high 20-bit resolution at a fast sampling rate of 1 MSPS and incorporating a reference buffer. In this case, the reference input doesn’t see any transients from the ADC. ADCs that incorporate an internal reference buffer reduce circuit complexity and allow the connection of multiple ADC devices to a single voltage reference, simplifying system calibration routines.

Figure 4

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High-performance SAR ADC incorporating a reference buffer.

High-performance SAR ADC incorporating a reference buffer.

A question you might ask is when the external reference buffer is required.

The buffer requirement depends primarily on two factors: the output drive capability of the reference and the SAR ADC input current demand. The SAR reference input current demand is a function of the sampling rate and resolution of the ADC. When designing a data-acquisition system, the first step is to check the SAR data sheet for guidelines; most data sheets provide an optimal circuit recommendation to support the maximum sampling rate. However, a detailed simulation analysis may be required depending on the sampling rate and reference used.

To learn more about SAR ADC reference drive circuits, see the TI Precision Labs – SAR ADC Reference Input series. This series provide a detailed step-by-step explanation on how to build your SAR ADC reference input SPICE model and verify reference driver settling using TINA-TI software.

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