DSP noise cancellation extends backplane reach

Analogix Semiconductor, a startup based in Santa Clara, has introduced what it believes are the first high-speed physical-layer transceivers to include built-in digital signal processing (DSP). The DSP techniques eliminate the signal integrity problems (noise, crosstalk, ringing and false triggers) associated with 5- and 10-Gbits/s data transmissions over backplanes and copper media.

The D-PHY family of SerDes ICs is based on a new architecture that combines an adaptive DSP-based noise-cancellation technique (which Analogix calls “WideEye” technology) with advanced analog signal conditioning. Unlike analog-only solutions, which simply mask detrimental signal effects such as crosstalk and reflections, the D-PHY family actually removes these effects, ensuring maximum signal integrity.

With noise problems eliminated over standard FR-4 backplanes and very-short-reach (VSR) system-to-system copper interconnects, the company claims system designers can:

*upgrade existing backplane systems with four-fold performance;

*design new, higher-speed systems with low-cost connectors and easily manufactured FR-4 materials rather than far more complex and expensive materials; or

*replace fiber-optic inter-system connections with much lower-cost standard unshielded twisted pair (UTP) or InfiniBand copper cable at distances of up to 50 meters.

The D-PHY family is designed for use in enterprise switches and routers, carrier-class transport equipment (including optical switches and cross-connects), Fibre Channel and IP- based storage systems, and high-end servers.

The first D-PHY products, D-PHY 5-Gbits/s backplane transceivers, are being announced April 5th. A 10-Gbits/s serial backplane transceiver family and a 10-Gbits/s serial interconnect over copper IC family will be introduced later this year.

Analog-only Approaches Can't Handle Noise at High Speeds

“The ubiquitous copper-based FR-4 backplanes in today's systems were designed when 5 Gbits/s speeds weren't even imagined,” said Ted Rado, vice president of marketing at Analogix. “Now designers of switches, servers, storage arrays and the like want more performance, but they want to get it by upgrading, not replacing, their existing systems. As vendors try to design new high-speed cards that fit into old FR-4 backplanes and interoperate with existing cards, they face major noise issues – not just signal attenuation but crosstalk and reflections. Since the backplane itself has a fixed number of traces, the burden is on the silicon to deal with the increased noise while pushing more performance through those traces.

“The same issues surface in system-to-system interconnect, where, even at distances of under 50 meters, copper media have severe noise issues at speeds over 1 Gbits/s,” Rado added. “Thus far, expensive, power-hungry fiber solutions have been the only choice.”

Analogix's D-PHY architecture, a mixed analog/DSP-based approach, is said to maximize signal-conditioning flexibility. Like traditional analog-based SerDes technology at 3.125 Gbits/s and below, D-PHY devices offer standard transmitter-programmable pre-emphasis and swing control. Up to now, companies targeting speeds beyond 3.125 Gbits/s have incorporated analog equalization at the receiver end, typically in the form of Decision Feedback Equalizers (DFEs). The D-PHY architecture's two chief elements – one analog, one DSP – offer significant advantages over such approaches:

First, analog signal-conditioning is provided by a multi-stage continuous-time linear equalizer. This has the benefits of DFE-based solutions, but with half the power consumption and die area. Analogix's implementation is said to also scale more effectively to 10 Gbits/s because its feedback loop does not occur at the maximum frequency.

Second, the WideEye technology includes adaptive equalization, adaptive reflection and crosstalk cancellation, and error correction coding. These techniques, not usually incorporated in backplane devices, help increase system vendors' design margins and flexibility in both upgraded and new designs. To address power concerns implicit in DSP technology, D-PHY chips offer a PowerSelect option, which lets users turn off individual WideEye functions for high-quality channels; this brings typical power consumption down to 2.9 watts or less.

D-PHY 5G Product: 6.25-Gbits/s Serial Performance on FR-4 Backplane

The D-PHY 5G backplane transceivers offer 1.25- to 6.25-Gbits/s serial transmission across up to 60 inches of standard FR-4 backplane material and two connectors. Two versions are available. The D-PHY 4x5G quad transceiver, with four high- speed links, provides up to 25 Gbits/s full-duplex transmission. The D-PHY 2x5G dual transceiver, with two links, performs at up to 12.5 Gbits/s. NRZ binary encoding on both devices ensures backward-compatibility with lower-speed Serdes transceivers. All D-PHY devices are compliant with the Optical Internetworking Forum's Common Electrical I/O (CEI) 6G+ specification.

Each D-PHY device also has eight low-speed (800 Mbps-3.125 Gbits/s) Serdes links. Flexibility is increased by three multiplexing options: 1:1, 2:1 and 4:1; a unique legacy mode available with 1:1 multiplexing detects connection with another Serdes device (e.g., a XAUI transceiver), allowing new cards to interoperate with existing ones. Comprehensive built-in self-test (BIST) functionality includes on-chip PRBS generators and error checkers as well as low- and high-speed loop-back paths for independent testing of all chip elements. D-PHY devices also offer real-time bit error rate (BER) monitoring capabilities by polling MDIO- or I2C-controlled WideEye DSP registers.

D-PHY 5G Pricing and Availability

The D-PHY 5G backplane transceiver is sampling now and will be available in production volumes in June. High-volume prices are $49 each for D-PHY 4x5G devices and $28 each for D-PHY 2x5G devices. The devices come in JEDEC-standard 260- pin HSBGA (Heat Slug Ball Grid Array) packages.

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