DVD Variation with Load Vector Delays

Spatio-temporal aspects of Dynamic Voltage Drop (DVD)

A recent Planet Analog article, Non-correlation of Peak Noise and Peak Current, discussed the complexity of reactive and resistive noise that combine to form dynamic voltage drop in a chip power grid. In that experiment, we saw how DVD varied with load waveshape, while peak load current stayed the same. Another experiment, exploring local power grid resonances, demonstrated DVD variance with changing load frequency. Again, peak load current remained constant, while spatial relationships between load currents and capacitance determined resonances. In the following experiment, we explore DVD variance with another aspect of PDN load currents. Here, we explore the temporal relationship between load vectors: time/phase delays between load maxima.

Why is this important to DVD optimization and sign-off? I have come across repeated instances in the past where chips have failed at the prototype stage. These complex systems incorporated numerous IP cores, DSP's and baseband processors, which share their PDN. The failure mode was invariably an activation regimen for the cores that produced large supply current spikes. And, these chips had passed through back-end sign-off verification for power integrity. Complex, nanoscale SoC's of the present are no doubt prone to such potential failures.

Besides, the EDA industry has sold a limitation, analysis sans vectors, as a feature for a decade or more. They've trained hapless customers to ask: “Do you have a Vectorless Analysis Engine? ” Sounds fancy, does it not? But what's a load vector without its timing and rate-of-change-with-time attributes? A stator, fit for multiplication with – Aha, that's (i⋅r drop ) the reason! – a static resistance value. Vectors also won't work correctly with a chip PDN model that breaks the speed of light. More limitations – that fit exceedingly well with an ingenious marketing tactic. I wrote about a necessary transition in 20084 !

I think it is crucial to investigate whether such approximations lead to accurate, dependable results.

Experiment Setup

Figure 1 below shows a complete PDN from a supply through board and package pathways and a chip power grid. Load blocks (charge consuming circuits) in purple, shown on the lowermost layer, connect to the chip power grid. They form distributed area loads, as it is in actual integrated circuits. Distributed capacitances, shown in parrot green on a layer above the load circuits, also connect to the chip power grid. The setup replicates the local resonance exploration experiment.

Note adjacent loads I1 and I3 in the PDN schematic. An identified resonance in this region of the chip PDN is near 5GHz. This resonance occurs when both I1 and I3 stimulate the PDN with the same load current wave. In this experiment, we vary the time delay between the two respective load waves. This is shown in Figure 2, which lists load stimulus ASCII files displaying 90° and 180° phase shifts for load current. Both peak load current and load spectral content remain unchanged from those at resonance.

Figure 1

Full PDN representation including chip/package power grids and board components.

Full PDN representation including chip/package power grids and board components.

Figure 2

Half-Sine 100mA load waves delayed by 50ps and 100ps (90o & 180o for a 200ps period).

Half-Sine 100mA load waves delayed by 50ps and 100ps (90o & 180o for a 200ps period).

Netlist and Simulations

Figure 3 shows PDN physical and electrical aspects captured in netlist form in PI-FP1 . Statement “Cchip1 0.0 0.0 0.07 0.07 400e-12” defines an area capacitance, with its origin at (0.0 0.0) of grid chip1, of 400pF capacitance distributed in an area of 0.07 by 0.07 CM. The chip1 grid is defined by a “Gchip1 …” statement included in the full simulation netlist, a portion of which is shown in the figure.

Load profile files ('pulse100gap250.profile,' for instance) in statements “Ichip1 0.1 …” and “Ichip1 0.02 …” change to manifest phase delay in this experiment. The netlist snytax, stimulus input, and the continuum simulator are described in detail in the Π-FP Manual .

Figure 3

PDN Netlist in Π-FP

PDN Netlist in Π-FP

Simulations in command-line mode complete in less than a minute on an i7 computer for each phase-delay condition. Manual changes to the netlist and simulation invocation hence sufficed to conduct this study. Figure 4 below displays derived results.

Figure 4

Maximum chip noise at resonance with phase delay between I3 and I1.

Maximum chip noise at resonance with phase delay between I3 and I1.

Discussion: DVD Variance with Local Interference

In the local resonance experiment, it was clear, visually, that the PDN response to I1 and I3 included interference. We noted a maximum chip DVD then of ∼ 49mV in a simulation span of 2ns. With a full sweep of phase delay, this peak-DVD value varied between 45.4mV and 49.2mV, or by as much as 8%. The adjacency of I1 to I3 on the same chip power grid hence has a notable impact on local DVD.

Phase differences of the I1 load vector with the I3 load vector are thus also instrumental in local DVD. Power grid wave propagation velocity and grid energy dissipation determine the nature and extent of interference. How then can DVD analysis that shuns these vector and PDN attributes be accurate ? Can a “Vectorless” exploration of PI degradation be efficient or optimal ?


  1. Yes , load vector phase differences, and power grid wave propagation, impact DVD1 .
  2. Peak DVD does not correlate with Peak-I when reactive, resonant, and propagated noise matter.
  3. Resonant and other noise components can add to chip DVD …and also create Rogue Waves 2 .

This experiment was created and run in Π-FP in its command-line mode.

For more on Π-FP, or such experiments, please contact us.


1 Raj Nair and Donald Bennett, Anasim Corp. “Power Integrity Analysis and Management for Integrated Circuits,” Pearson Education – Prentice Hall, 2010.

2 M. Hashimoto and Raj Nair, “Power Integrity for Nanoscale Integrated Systems,” McGraw Hill, 2014.

3 Raj Nair, Anasim Corp. “IC Floorplanning and Power Integrity,” SOCcentral 2010.

4 Raj Nair and Donald Bennett, Anasim Corp. “Beyond IR Drop: Dynamic Voltage Droops and Total Power Integrity,” March 2008.

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