NETANYA, Israel Startup Micrologic Design Automation Inc. (Haifa, Israel) has released what is claims is the first nanometer range EDA tool that interactively eliminates reliability issues during the early stage of the physical design.
Micrologic's founder, president and CTO Dr. Danny Rittman told EE Times Europe that the startup is aiming to raise $5 million in order to market the software in the U.S., Europe and Japan. “Reliability is becoming a hotter issue as we move from 90-nm and 65-nm designs to 45-nm and 32-nm designs in the future. From 90-nm and lower, our technology is a must have,” said Rittman.
The tool, dubbed nanoRVInteractive, automatically analyzes design for reliability parameters, including but not limited to electromigration, self heat and voltage drop (IR Drop) during the construction of IC layout, and creates a Reliability-Aware mask design environment. The tool is offered under Micrologic's NanoToolBox productivity suite, and is a plug-in into Cadence Virtuoso custom design platform.
According to Rittman, NanoRVInteractive is a whole new concept in verification: reliability aware design environment. “All we have today is sign-off tools such as Cadence's Voltage Storm and Mentor Graphics' Calibre products. These tools force you to spend valuable time in checking a block only after it had been designed, and then go back and correct your design if necessary. Our tools enable reliability check in early design stages and shorten the time to tapeout by months, if not years.”
The other EDA tool that Micrologic is set to offer is VisuaLVS, which automatically corrects connectivity mismatches in a chip's layout block. The tool reads the IC layout block's industry standard LVS check results, its netlist and constraints and automatically corrects connectivity mismatches, maintaining the process design rule correctness.
In addition, VisuaLVS supports timing and DFM along with process topological rules providing a real-time LVS correction environment. VisuaLVS is also offered under NanoToolBox(NTB) tools suite and is a plug-in into Cadence Virtuoso custom design platform.
“An engineer that designs a block in one week will typically spend one and a half days for manual LVS (Layout Versus Schematic) and DRC (Design Rule Check) in order to 'clean' the block,” said Rittman. “We can shorten this period to five minutes. You click a button and the software automatically corrects what is needed in the design.”
According to Rittman, Micrologic's tools have been evaluated by several companies such as Tower Semiconductor, E2V and Sequoia Communications and are set to be evaluated by STMicroelectronics this month.
“We are in the process of raising $5 million for sales, marketing and support for our products,” Rittman added. “In the next few weeks we will also be targeting the Japanese market, in which there is demand for our products since June last year.”
Micrologic was established in 2006 and employs workers in Israel, in West Hollywood, California and in Europe. The company received seed money from Euroweb International Corp., in return for an equity in the Micrologic.