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Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A

ABOUT THE AUTHOR

Nitin Mohan received his B.Tech. in Electronics Engineering from Institute of Technology-BHU, India in 1999 and MA.Sc. in Electrical and Computer Engineering from University of Waterloo, Canada in 2001. From 1999 through 2000, he was with Wipro Technologies, India where he designed and verified ASICs/FPGAs. Since 2001, he is with Sirific Wireless, Canada where he designs CMOS ICs for wireless standards.

Verilog-A provides a new dimension of design, simulation, and testing capability for electronic systems. You can use the powerful features of Verilog-A language for fast testing of analog and mixed-signal systems. The analog and mixed signal languages, such as Verilog-AMS, VHDL-AMS and Verilog-A, are primarily viewed as simulation tools for mixed-signal and mixed-domain systems. However, you can use their versatile features in the system-level abstraction and testing of analog ICs equally well.

The behavioral descriptions in these languages are very economical in terms of simulation time and memory requirements. Considering the pressing short product-to-market time requirement in today's highly competitive market, it becomes essential to use these languages for quick testing of large system-on-a-chip (SoC) designs which contain analog circuitry, digital-logic blocks, memories, and processing capability on the same piece of silicon.

VHDL-AMS and Verilog-AMS are supersets of VHDL and Verilog HDL, respectively. Besides the digital components, these languages also support analog behavioral constructs. Verilog-AMS is still in the development phase, but its analog subset is standardized and known as Verilog-A. However, the EDA tools that support AMS feature are expensive and are mostly in the development phase. Cadence tools support mixed-signal simulation, but they require the licenses of both the Verilog simulator and the analog simulator (SPICE/Spectre), which can be expensive for small companies, especially if they are needed only for a couple of projects.

Small companies developing analog and mixed-signal ICs may need to implement small digital blocks on the same chip. These digital blocks may contain a few thousand transistors and consume a lot of simulation time if simulated in SPICE/Spectre. The Verilog-A behavioral code can replace the digital circuitry and reduce the simulation time dramatically. The powerful analog solver of SPICE/Spectre can readily simulate a system with analog-circuit schematics and Verilog-A blocks. You can convert Verilog-HDL behavioral code to Verilog-A code after some modifications, which this article discusses.

Several semiconductor companies provide Verilog models of their products for simulation purposes. In addition, most of the common digital blocks are freely available on the World Wide Web in the form of Verilog HDL models. If these Verilog HDL codes are converted to Verilog-A, they can be extremely useful for testing the analog ICs, particularly the ICs under development. Furthermore, this savings of simulation time comes at no extra cost since the Verilog-A simulations do not require the digital HDL simulator; the existing Spectre license can be utilized for this purpose. This article explores two important features of the Verilog-A language:

  1. Conversion of Verilog-HDL models to Verilog-A models
  2. Applications of Verilog-A constructs in the quick testing of analog and mixed-signal ICs.
Verilog HDL to Verilog-A

Verilog HDL, commonly known as Verilog-Digital or Verilog-D, simulators proceed with the discrete change in signals at discrete points in time. However, Verilog-A simulation takes place in the analog domain and all the differential algebraic equations (DAEs) are solved at every point in time. The generalized form of Kirchhoff's Potential and Flow laws (KPL and KFL) formulates the DAEs.

Converting Verilog-D to Verilog-A code can be a non-trivial task. Each model may require a different approach, yet some of the general guidelines can be followed to make the process systematic. In Verilog-D, an 'initial' statement is used to perform the actions only at the beginning of the analysis. This can be replaced by an 'initial_step' event in Verilog-A. Similarly, an 'always' block in Verilog-D can be replaced by 'cross' block in Verilog-A. The @timer(start, period) statement can generate a clock using the @timer(start, period) statement, which generates an event at time 'start' and repeats it after every 'period'. Like Verilog-D, Verilog-A can pass parameters to customize the general modules in the code. Parameters are constants and their values cannot be modified during the runtime; they can only be changed during compilation. The following example illustrates some of the above statements:

// Module declaration

module mixed

// Port declaration

input Clk;

electrical Clk;

input Reset;

electrical Reset;

...

// Parameter declaration

parameter real VDD = 1.8;

parameter real period = 1.0E-6;

// Internal variables declaration

real var_int1, var_int2;

integer clk_int;

...

// Analog block

analog begin

@(initial_step) begin

   var_int1 = 0.0;

   var_int2 = 1.8;

   clk_int = 1;

end

// Internal clock generation

@(timer(0, period/2))

   clk_int = -clk_int;

// Detection and processing of the cross events

@(cross(V(Clk) - 0.5*VDD,+1) or cross(V(Reset) - 0.5*VDD,+1))

begin

...

end

end

endmodule

Here +1 shows the positive edge of the clock. Similarly, -1 and 0 are equivalent to 'negedge' and 'edge' respectively. You can replace the wire assignments in Verilog-D by contribution statements in Verilog-A. For example:

Verilog-D: assign Ndecode = N;

Verilog-A: V(Ndecode) <+ transition(N,0.0,1.0n);

You can replace internal registers and wires in Verilog-D by real and integer numbers, along with their arrays. Verilog-A also supports most of the conditional statements (ifelse, case, while). The input and output pins (registers and wires) of a Verilog-D model are converted to electrical pins in Verilog-A. The input pin voltages can be registered to the internal variables (real and integers) at every positive edge of the clock using @(cross()). Now these variables can be processed using the conditional blocks and mathematical functions supported by Verilog-A.

The user can also define functions for reusability and better code readability. The contribute statements can assign processed variables to the output pin voltages. However, the processing of vectors can be a non-trivial task in Verilog-A. For example, if we have an input pin which is a binary vector N[3:0], in the Verilog-A model, we can register it to an array of real n[3:0]. Now, if we want to increment this vector by one in the original Verilog-D code, we can simply write

N = N + 1;

But this is not that straightforward in Verilog-A. You need special algorithms to perform vector operations. For example, you can perform the prior operation using the following code in Verilog-A:

....

if (n[0] == 0.0)

   n[0] = 1.8;

else if (n[1] == 0.0)

begin

   n[1] = 1.8;

   n[0] = 0.0;

end

else if (n[2] == 0.0)

begin

   n[2] = 1.8;

   n[1] = 0.0;

   n[0] = 0.0;

end

else if (n[3] == 0.0)

begin

   n[3] = 1.8;

   n[2] = 0.0;

   n[1] = 0.0;

   n[0] = 0.0;

end

....

You can apply a similar algorithm for a decrement-by-one operation as well. Note that in this case logic '1' refers to a voltage of 1.8 V.

Applications in Testing

You can also use the flexibility and speed of Verilog-A codes in the quick testing of analog, mixed-signal, and mixed-domain circuits. This is particularly useful at the system-design level. You can test a new idea with the existing circuits just by adding a Verilog-A block which you can modify depending of the fine tuning of the idea. In addition, you can test the system for any arbitrary set of stimuli generated by Verilog-A models, which can test the robustness of the system under adverse conditions. Furthermore, Verilog-A's capabilities go beyond the electrical domain and can easily accommodate the thermal and optical domains. This expanded capability can provide a more realistic system abstraction that is not always possible in circuit-schematic-level simulations.

In Spectre simulations of large analog and mixed-signal ICs, you can replace some of the analog blocks, which are complex at transistor level but simple at the behavioral level, by their Verilog-A counterparts to reduce simulation time. In addition, simulation of some of the commonly used digital blocks, such as counters, adders, multipliers, and so on, are much faster in using their behavioral models than with transistor-level circuit schematics. Cadence custom IC development tools include a model writer that can automatically generate the Verilog-A models for some of the commonly used IC components. In addition, system tasks '$realtime()' and '$temperature()' can access the simulation's environmental conditions, such as the instantaneous time and ambient temperature. You can use these tasks to generate independent signal sources and temperature-dependent models respectively. For example:

...

Vi = A*cos(2*`M_PI*Fosc*$realtime());

Vq = A*sin(2*`M_PI*Fosc*$realtime());

...

Furthermore, during DC analysis, the output pins can be forced to a given set of values passed by the parameters using the 'analysis()' function. For example:

...

if(analysis("dc"))

   Out_pin <+ dc_out;
else

   Out_pin <+ tran_out;
...

Simulation Results

We simulated two mixed-signal circuits at the full transistor schematic level and with the digital blocks replaced by their respective Verilog-A models. A dramatic improvement in the simulation speed is observed. Tables 1 and 2 show the simulation results. In Table 1 , a block with 166 transistors out of total 436 transistors is replaced by its Verilog-A model and the simulation speed increased by more than ten times. In Table 2 , a digital block with almost 6500 transistors is replaced by its Verilog-A model and the simulation speed is increased by 1000 times, which is remarkable. The improvement in simulation speed depends mostly on the complexity of the algorithm used to model the block in Verilog-A. Thus, the block abstraction should be done as simply as possible to minimize the simulation time.

Cell View No. of
Transistors
No. of
Equations
Simulation Time
Schematic 436 1111 52 s
AHDL 270 697 4 s

Table 1

Cell View No. of
Transistors
No. of
Equations
Simulation Time
Schematic 7000 17601 125 ks
1 day, 10 hours, 42 min.
AHDL 439 1148 124 s

Table 2

Conclusions

The previously described results demonstrate the usefulness of Verilog-A in testing analog and mixed-signal ICs and in fine tuning of the system-level abstraction. Considering the ever-increasing number of transistors on a chip and SoCs with analog, RF, and digital modules on the same chip with newly proposed architectures, you can use Verilog-A for initial testing and verification in an economical and convenient way. The conversion of Verilog HDL models to Verilog-A models provides additional flexibility in terms of simulation tools. This can be cost effective for designers who are working on R&D projects with limited resources. This article has highlighted only a few of the applications of the Verilog-A language. The scope of the other possible capabilities of Verilog-A is immense and can be explored by the designers, depending on their own requirements and insights.

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