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eGaN Technology Reliability and Physics of Failure Blog #3

eGaN® Stress Test Qualification and Capability

The first two installments in this series reported in detail on field reliability experience of Efficient Power Conversion (EPC) Corporation’s enhancement-mode gallium nitride (eGaN®) FETs and integrated circuits (ICs). The excellent field reliability of eGaN® devices demonstrates stress-based qualification testing is capable of ensuring reliability in customer applications. In this installment we will examine the stress tests that EPC devices are subjected to prior to being considered qualified products.

EPC products are considered production ready only if they are able to withstand a rigorous set of stress-based qualification tests, while continuing to operate within datasheet specifications. To ensure product reliability in end-user applications over expected operation lifetimes, stress tests are used to accelerate potential failure modes. All EPC products are qualified according to Joint Electron Device Engineering Council (JEDEC) stress tests, which are intended for power FETs, ICs, and chip-scale packaging. EPC stress test qualification can be grouped into three main areas, intrinsic die, package environmental, and board-level reliability.

Table 1 below provides an overview summary of qualification test results including sample size, equivalent device hours, and statistical estimate of failure rate. Additional qualification data for specific products or product families can be found on the EPC home page: eGaN® FET Reliability .

The sections that follow will go into more depth explaining the qualification stress tests and objectives.

Table 1

Summary of Composite Upper Bound Failure Statistics

Summary of Composite Upper Bound Failure Statistics

Intrinsic Die Qualification

Figure 1 shows the basic structure of the eGaN® power transistor. The device is a three terminal lateral structure, in which current flows from source to drain along a two dimensional electron gas (2DEG). Normally, the 2DEG is depleted under the gate resulting in an off state condition. When a positive bias voltage is applied to the gate terminal, the 2DEG is enhanced and fills in under the gate completing the conductive path from source to drain.

Figure 1

eGaN® power transistor basic structure

eGaN® power transistor basic structure

Voltage and temperature are most commonly used to accelerate stress conditions within the die. Elevated voltage and temperature over many hours can be translated to predict reliable operation in terms of years within customer application circuits. High Temperature Gate Bias (HTGB) is the standard test used to examine the reliability of the device under applied gate stress. The device is set to the off state (drain shorted to source) with gate-source bias voltage (VGS ) ≥ 80% maximum rated, and maximum rated junction temperature (Tj ) applied.

High Temperature Reverse Bias (HTRB) is used to evaluate reliability in the off state under high drain bias condition. The device is biased in the off state (gate shorted to source), with drain-source voltage (VDS ) set to ≥ 80% maximum datasheet rating at maximum Tj . All device parametric parameters including leakage current, threshold voltage, and on-state resistance (RDS(on) ) are monitored for device stability.

EPC has accumulated a large set of HTGB and HTRB data demonstrating the intrinsic reliability of eGaN® FETs and ICs. The data shows these devices are on equal footing or even more reliable than their silicon counterparts. In fact, military and space (radiation hardened) applications are on the forefront of GaN adoption, which would not be possible without a high level of confidence in reliability standards established.

Package Environmental Qualification

The capability of the die and package to withstand environmental conditions to which the products are exposed during shipping, storage, customer assembly, and system applications are examined with another set of reliability stress tests. In addition to voltage and temperature acceleration, humidity and peak solder reflow temperature stresses are applied. Figure 2 shows an example of an eGaN® FET in the chip-scale package. The device’s active layers are well protected from the surrounding environment by glass passivation.

Figure 2

EPC2032 top layer passivation and solder bumps

EPC2032 top layer passivation and solder bumps

EPC products are qualified with the following set of environmental stress tests:

  • High Temperature Storage (HTS): Devices stressed at maximum rated temperature.
  • High Temperature High Humidity Reverse Bias (H3TRB): Devices stressed with elevated humidity (85% RH), drain-source voltage ( ≥ 80% max rated), and 85o C temperature.
  • Autoclave (AC): Devices stressed with elevated pressure (29.7 PSIA), humidity (100% RH), and temperature (121o C ).
  • Moisture Reflow Sensitivity (MSL): Devices stressed at elevated humidity (85% RH) and temperature (85o C ), followed by 3 passes of solder reflow temperature profile.

EPC chip-scale packages are qualified as Moisture Sensitivity Level 1 (MSL1), with unlimited shelf life capability. Without additional material (e.g. plastic mold) surrounding the glass passivated die chip-scale package, reliability concerns such as moisture ingression are nearly eliminated. Devices with fine pitch outlines are closely monitored during stress tests such as H3TRB, where the potential for dendrite growth to form and bridge solder balls exists.

Board-Level Reliability

All EPC devices undergoing qualification stress tests are solder mounted to individual printed circuit board (PCB) device under test (DUT) cards. DUT cards are used to help with handling and parametric testing of these small die size devices. The added benefit of performing all stress testing with devices mounted to DUT cards is the opportunity to test board-level reliability in parallel.

Thermo-mechanical tests are used to stress the attachment interfaces between the device and the PCB. Temperature Cycling (TC) is done by exposing the devices to alternating cycles of cold and hot ambient temperatures without bias applied. Intermittent Operating Life (IOL) stress test applies a fixed power to the device to raise the junction temperature to a predefined temperature and subsequently the power is removed to cool the junction to starting temperature. The cyclic temperature variation causes varying thermal expansion and contraction within the die, solder bumps, and PCB. For chip-scale packages solder joint fatigue and cracking is the result of such stresses, and is the primary metric to evaluate board level reliability. Figure 3 shows the effect of a device taken to failure by thermo-mechanical stress.

Figure 3

Cracked solder joints resulting from IOL stress testing (Δ Tj = 100o C)

Cracked solder joints resulting from IOL stress testing (Δ Tj = 100o C)

Beyond the standard set of stress tests described above for product qualification, EPC performs additional reliability investigations such as Electrostatic Discharge (ESD), Early Life Failure Rate (ELFR), and electromigration (EM). These additional stress tests, together with product qualification testing, are targeted to evaluate reliability over the full product lifetime, including infant mortality and end of life wear-out.

JEDEC-based stress tests described here are used to qualify and define capability of eGaN® devices, however field reliability ultimately provides the measure of device capability while operating in end user applications. This report, together with previous installments, shows eGaN® FETs and ICs are capable of surpassing industry reliability standards both during qualification and when deployed in the field. The next report will discuss accelerated stress tests, acceleration factors, and physics of failure, providing more insight into eGaN® product capability over operation lifetime.

eGaN is a registered trademark of Efficient Power Conversion Corporation

3 comments on “eGaN Technology Reliability and Physics of Failure Blog #3

  1. dick_freebird
    July 11, 2016

    I have two concerns about EPC's devices which this article and the
    qualification regimen do not address.

    First, a few years back the bug-a-boo was a destructive gate overvoltage (and/or overcurrent) induced failure mode which was right about 5V, such that you could not “just use a 5V supply and 5V driver” and be confident that some eventual supply transient or drift wouldn't punch out the transistor. Saw some stuff about that being worked on while I was designing an eGaN driver (with measures against such an event). Have not seen anything like the triumphal announcement I'd have expected if the problem were fully understood and solved. Is it?

     

    Second, while moisture is interesting, mobile ionic contaminants are the main reason encapsulation is wanted. Certainly silicon CMOS and some bipolar are sensitive. What has been done to “challenge” the eGaN structure with sodium, potassium, other mobile species and prove some degree of immunity?

  2. c_jakubiec
    July 12, 2016

    Thanks for inquiring into EPC devices.

    eGaN device gates are capable to withstand 6V bias. The gates have been shown to be extremely reliable when operated within the datasheet specifications, and gate reliability data is available in previous blogs as well as the EPC website.

    Mobile ion contamination has been identified as a problem in silicon devices many years ago, and is mainly due to the gate oxide layer where these unwanted charges can accumulate. eGaN devices do not have a gate oxide insulator layer, and there is no evidence that mobile ions effect our products. In addition to modern fabs and clean rooms that have significantly reduced the threat of these types of contaminants, EPC chip-scale packages use passivation layers such as silicon nitride to prevent such issues.

  3. vnaisualal
    July 13, 2016

    its great one post

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