eGaN Technology Physics of Failure
The previous installment in this series focused on the physics of failure surrounding thermo-mechanical reliability of EPC eGaN wafer level chip-scale packages. A fundamental understanding of the potential failure modes under voltage bias is also important. This installment will provide an overview of the physics of failure associated with voltage bias at the gate electrode of gallium nitride (GaN) field effect transistors (FETs). Here we look at the case of taking the gate control voltage to the specified limit and beyond to investigate how eGaN FETs behave over a projected lifetime.
eGaN FET Basic Structure – Lateral Enhancement Mode
The basic lateral eGaN transistor structure is shown in Figure 1. The gate (G), source (S), and drain (D) terminals are arranged like a typical field effect transistor. The device is formed starting with a silicon wafer followed by growth of a gallium nitride heterostructure, which results in an enhancement mode device which is normally off (non-conducting) with no bias applied .
The conducting channel is formed by growing a thin AlGaN layer on top of the high resistance GaN layer. The AlGaN to GaN interface creates a strained piezoelectric effect, where a two-dimensional electron gas (2DEG) of abundant high mobility electrons exist. The gate electrode forms a depletion region in the 2DEG to block the conducting channel in the off-state. Protection dielectrics and metal routing form the top layers of the device.
The FET is enhanced to the conducting on-state with the application of a positive voltage at the gate electrode, similar to the operation of a silicon n-channel enhancement mode power FET. The power FET is formed by connecting many of these basic cell structures in parallel.
eGaN FET basic cell structure.
Figures 2 and 3 show the gate-to-source bias (VGS) transfer curves and on-state resistance (RDS(on) ) vs. gate voltage representing a typical eGaN FET . The voltage level to achieve turn-on threshold and subsequent transconductance as a function of drain current is shown in Figure 2. Figure 3 shows the conducting channel is fully enhanced near a gate voltage of 4 V, as the corresponding on-state resistance remains relatively flat beyond that point. Absolute maximum gate-to-source voltage of 6 V ensures safe operation.
Transfer curves for EPC2016C
RDS(on) vs. VGS at various currents for EPC2016C
Gate Voltage Stress Reliability
High Temperature Gate Bias (HTGB) stress test is the industry standard to evaluate the reliability of FET gate structures. HTGB testing is performed by connecting the source and drain terminals to 0 V, applying a voltage to the gate, and setting the ambient temperature to maximum rated junction TJ . Voltage and temperature are both used to accelerate operating stress conditions.
High gate voltage stress can lead to three principal failure modes in GaN gates: dielectric failure, rupture of the gate sidewall, and gate bias induced drain leakage current. These are indicated schematically in Figure 4. Dielectric breakdown results from high electric field in the protection dielectric surrounding the gate; this failure mode is akin to oxide breakdown mechanisms that occur in MOSFETs. Sidewall rupture is an avalanche breakdown mechanism that occurs from field crowding at the vertical edge of the gate near the gate metal. This failure mode can be controlled with proper surface passivation and electrostatic design. The predominant gate failure mode observed for eGaN FETs operated at high gate voltages is the increased off-state drain leakage current. This is caused by localized charge migration and trapping in the GaN gate. Though the trapping occurs when the gate is biased on, it leads to a slow increase in source-drain leakage current when the part is in the off-state. Experiments show the leakage current is highly accelerated by the electric field resulting from the gate voltage bias.
Electric field magnitude inside an eGaN gate at VGS = 5 V. The main failure modes, exacerbated by high electric fields, are indicated as well.
The voltage dependent acceleration of HTGB failures was investigated by conducting a matrix of tests at gate voltages between 6 V and 7 V, while maintaining a constant temperature of 150o C (note: VGS = 7 V is beyond the recommended safe operating range of eGaN FETs). The gate test voltage was limited to 7 V as to not induce additional failure modes such as sidewall dielectric ruptures. Three gate voltage legs consisting of 32 EPC2016C (datasheet: VDS(max) = 100 V, VGS(max) = 6 V) FET devices per leg were tested. The devices were subjected to HTGB stress test with incremental read points at 24 hrs., 100 hrs., and 200 hrs. The read point measurements consist of DC datasheet parameters. Time to failure was measured in-situ via periodic parametric monitoring of the devices at 2 minute intervals. The failure criteria are the off-state drain current or gate leakage current exceeding the datasheet limits.
Weibull fits were used to estimate mean time to failure (MTTF) and failures in time (FIT), as seen in Figure 5 and Figure 6. Error bars represent uncertainty resulting from 90% confidence intervals of the Weibull parameters. The green line in the graphs represents a best-fit exponential acceleration function. Taking the gate voltage limit of 6 V from the datasheet predicts the MTTF to be well above a period of 10 years at 150o C.
HTGB voltage acceleration stress test – mean time to fail vs. gate voltage (EPC2016C) @ 150o C.
HTGB voltage acceleration stress test – FIT rate vs. gate voltage (EPC2016C) @ 150o C.
Gate Stress Test Results
High temperature gate bias stress testing is required for all EPC production released device families. A large set of HTGB data has been accumulated spanning the product voltage and die size range. The tables below show the composite summary statistics of gate stress testing including long-term testing of 1000 and 2000 hours, and early life failure rate (ELFR) evaluation that looks for failures after just 48 hours in large sample sizes .
HTGB summary statistics – calculations assume acceleration factor AF = 1 at 150o C
Field reliability as covered in detail of previous installments 1–3, confirms eGaN FET gates are reliable in end user applications. A summary of field failures by root cause category is shown in Table 2. Device degradation failures were due to a drain-to-source overvoltage condition, resulting in a shift of the RDS(on) because of carrier charge trapping. As of this installment, EPC has not recorded any field failures due to gate voltage bias in operation. Over 30-billion total field device hours with no gate failures equates to a very low projected failure rate of 0.03 FIT at 60% confidence.
Field failure summary – failure types and quantities
GaN transistor failure modes and underlying physics of failure during in-circuit operation conditions are important to predict device reliability and lifetimes. This installment provided insight into how eGaN FETs are expected to behave as the result of high gate voltage stress conditions. Reliable operation over many years can be expected for devices that are operated within recommended datasheet specifications. The next and final installment will provide a summary of this series presented on eGaN technology reliability and physics of failure.
 C. Jakubiec, R. Strittmatter, C. Zhou, “EPC eGaN FETs Reliability Testing: Phase 8,” 2016.
 Alex Lidow, Johan Strydom, Michael de Rooij, David Reusch, GaN Transistors for Efficient Power Conversion, Second Edition, John Wiley and Sons, 2015.