ESD Protection for Analog Circuits

Static electricity can be one of those things that can leave both analog and digital circuits out of commission. Static electricity often occurs when dissimilar materials rub against each other causing charge to build up on the surface of the objects. When this discharges into an object this is known as electro-static-discharge (ESD).

ESD can be upwards of 25KV with low amounts of stored charge, and high source impedances. There are many different methods for qualifying equipment against ESD. Some include the ubiquitous CE mark that is common on consumer goods. Other standards exist for automotive, aircraft, medical, industrial, and other types of equipment.

Protecting against ESD depends on the level of ESD exposure expected, and the market and industry constraints. Devices and methods include:

Spark-gap: In this method there is a gap between two electrodes in free-air, PC board traces, connector contacts, two or three electrodes in a gas-discharge tube (GDT), or other conductors. This air or GDT gap allows the bulk of the ESD discharge to jump to ground. “Ground” may refer to an actual galvanically bonded connection to the earth or simply to circuit common. PC board gaps are common in low-cost consumer goods. GDTs are more common in telecommunications, computer, and industrial equipment. GDTs are filled with an inert gas so that they will have a very predictable breakdown voltage.

As might be guessed regarding the PC board method, layout techniques are often quite critical in getting good ESD performance in devices. Additionally, it is often a good idea to put a perimeter trace around the board edge flashed with non-corrosive metal tied to ground to minimize problems from shop handling.

Series resistance: In this method, series resistance is added to an I/O line to impede the ESD discharge. The result is a voltage drop and reduced current flow. This often is combined with Schottky diode clamps to the power supply rail and ground. Sometimes the clamping diodes are internal to the device being protected.

MOV: The metal oxide varistor (MOV) is another low cost method for ESD and for surge protection. These devices are voltage variable resistors that exhibit a sharp drop in resistance as voltage increases past a certain point. Functionally, they act similar to a Zener diode with a few caveats: They are bipolar; they have very loose voltage tolerances; they wear out with exposure to overvoltage conditions. When they finally wear out, they fail open. They can also add significant capacitive loading to signal lines. But they are low cost.

TVS/TVS arrays: The transient voltage suppressor (TVS) is another frequently used method of ESD protection. These devices are functionally Zener diodes, but with a much larger P-N junction area. As a result, they will tolerate significant reverse current with only minor degradation. These will fail short circuit in the event of overstress. The TVS comes in a wide variety of sizes and styles ranging from miniature BGA arrays for cellphone I/O protection to massive devices used for power input and mains input protection.

Good decoupling: This prevents ESD from “ringing the power rails” and causing analog or digital control circuit malfunctions. Such malfunctions can manifest as sporadic and unpredictable resets or toggling of digital circuits.

Shielding: Shielding around sensitive circuitry can help. Circuitry that may benefit from shielding includes high-gain, wide bandwidth amplifier stages, voltage references, and the inputs to data converters. The ADCs' analog input is sensitive of course, but the clock and data lines to DACs and multiplexers (muxes) can also suffer. If you have control over set-up time, that can prevent ESD glitches from doing things like confusing the DACs and switching muxes to an incorrect channel.

Good power and ground planes: These can shunt ESD into the decoupling network and prevent damage or upsets in circuits.

What ESD-related phenomenon have you seen? Are your designs fairly robust or do you find yourself with a few head scratchers in qualification? Any other methods you use with sensitive analog circuits?

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11 comments on “ESD Protection for Analog Circuits

  1. RedDerek
    August 10, 2013

    Nice basics on ESD protection. The methods mentioned also aid for digital as well.

  2. samicksha
    August 12, 2013

    I guess most common example of a natural spark is lightning, wherein the electric potential between a cloud and ground, or between two clouds, is typically hundreds of millions of volts, also not to miss due to it gets more complicated when we look at the concern that dielectric nature of electronics component and assemblies, electrostatic charging can not be completely prevented during handling of devices.

  3. Davidled
    August 12, 2013

    ESD Gun which set 0.5KV to 30KV might use for ESD testing. High voltage could be programmed in the tool.  Be carefully for using ESD Gun not to touch board by hand while shooting the device by Gun.

  4. Netcrawl
    August 13, 2013

    Thanks for a great article, as IC process-technology nodes continue to evolve and get smaller, they become increasingly more susceptible To ESD damage, not just in manufacturing process but also in the real-world environment. 

    Gadgets like smartphones, laptop and computers introduce could introduce a more severe level of ESD, its is important to know that survival through the manufacturing process does not guarantee survival in the real-world environment, an ESD protection like ESD supressors, may be ncessary its a good idea to have this. 


  5. samicksha
    August 14, 2013

    I am curious understand about design challenge. As the average pin count for modern ICs increases to above 3000 pins, the total stored charge increases, which translates into a significantly increased peak ESD current.

  6. Hughston
    August 15, 2013

    The most important basic step is good physical isolation of the electronics and good EMI design. Use insulating materials in the mechanical design to increase isolation.  Insulate around displays, keypads and buttons especially. Beware of ESD strikes jumping through metal or through air holes in the enclosure to the PCB.  Another important step is pay attention to your reset circuit.  Avoid long traces. Use an ESD guard trace around the perimeter of the PCB, but this can cause induced failures. MOVs are not as good as transzorbs and low capacitance protection devices for lightning and ESD. Beware of excess lead length if you have leaded components. ESD can jump to a lead. Keep traces away from the perimeter of the PCB and round pads and traces near the perimeter.

  7. Brad_Albing
    August 23, 2013

    @DaeJ – I think there are detailed protocols and test techniques set out in the various standards that describe precisely how these ESD tests are to be performed.

  8. Brad_Albing
    August 23, 2013

    @samicksha – depends on where the charge is accumulated. More to the point, if you have an IC with that many pins, you'd need to add lots of ESD protection to all of them. But maybe not all would need the same amount of protection. Peak voltage and current levels may vary.

  9. Brad_Albing
    August 23, 2013

    @Hughston – you're hitting on an important consideration – where does the current flow from/to during an ESD event. And what effect does that have regarding inducing voltage gradients and current flows in nearby conductors.

  10. Hughston
    August 26, 2013

    A good question my friend.  I think ESD is trying to go to power or ground. If you have a wired connection to outside the box or system; ESD wants to go out on that wire and you get a higher current if your system is wired to the outside world rather than isolated. If you test a hand held battery powered device that is not hooked to a charger, that is an easy device to protect because the current won't be high unless it has somewhere to jump to through the device. Like for example, if you test the device on a metal table instead of a insolated table. You want ESD protection devices to take you to the system power, ground or a big cap as soon as possible. If you have an ESD protection device at an interface port, put a large cap on its power to ground connection. On thing you'll notice on some of these external interface ports is longer ground connections. That has a dual purpose. You want to make the ground connection first for electrical reasons, but you also want ESD hits to go to ground.

    Sometimes a capacitor is good protection for ESD against induced failures. The capacitor can act as a high frequency filter for induced voltages. This technique was used for resistive touchscreens and MOSFET gates.

    To answer your question about the voltage gradient, you want to get the ESD current to the system single point ground for the power. You have the biggest cap there and it keeps the ESD from getting there through a processor or other sensitive chip. Here is another point: if you have an isolated wall wart, the ESD will blow right through it. After many hits the insulation breaks down and the current keeps increasing and makes the system more sensitive.

    One advantage engineers have today is that chips have much better ESD immunity than back in the 80s when these problems started getting noticed. Back then you had to try different vendors for ESD immunity. Today with chips so specialized, you wouldn't have than luxury.

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