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Extreme Design: Realizing a single-chip CMOS 56 Gs/s ADC for 100 Gbps Ethernet

To provide a long-haul, 100-Gbps, optical transport network with maximum reach and immunity to optical fiber non-idealities, the industry has settled on dual-polarization quadrature phase-shift keying (DP-QPSK) as a modulation method, which means that a coherent receiver is required. The biggest implementation challenge resulting from this decision is the need for low-power ultra-high-speed ADCs, and their technology requirements define the way that such a receiver can be implemented.

A 100-Gbps coherent receiver needs four 56-Gs/s analog/digital converters (ADCs) and a tera-OPS DSP which dissipate only tens of watts. This paper discusses the forces pushing towards a single-chip CMOS solution, and the challenges in realizing this.

Without suitable ADCs – especially with low enough power consumption – it is impossible to produce a 100Gbps coherent receiver suitable for a commercial optical network, as opposed to prototype systems only suitable for demonstration in the lab.

These ADCs need sampling rates of at least 56 Gs/s and resolution of 6 bits or more, with power consumption of no more than a few watts each to fit within the power constraints imposed by the system. To do this with sufficient dynamic range for input signals up to 15GHz and higher, it was thought that this would require technology such as very advanced SiGe or ultra-small-geometry CMOS (40nm or smaller). By extrapolating from historic advances in ADC design, it was predicted at the end of 2008 that suitable ADCs would not be available until 2013.

However, the development of new circuit techniques means that these ADCs actually became available in 2009 using 65nm CMOS. This brought forward the date at which single-chip 100-Gbps coherent receivers became technically and economically feasible, and has caused a significant change in the industry roadmap for these devices.

This Extreme Design article discusses the underlying design issues, how the design was implemented, and the Fujitsu’s first customer evaluation technology containing a two-channel 56-GSa/s version of the ADC. It is presented in pdf format (no registration required); to read it, click here .)

(Editor's Note : to see the previous articles in the “Extreme Design” series, click here .)

About the author
Ian Dedic is with Fujitsu Microelectronics Europe GmbH, Maidenhead, Berkshire, United Kingdom.

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