(Editor's note: This is the second in a series of Extreme Design stories, where we look at design issues and tradeoffs at the system level, for applications where one or a few objectives dominate and define the design challenge. There is a link to the previous story in this series at the bottom.)
New generations of defense imaging systems, using sophisticated sensor technologies, generate invaluable information for modern warfare. On large platforms, such as ships, planes, or ground vehicles, the systems use onboard integrated-computing engines that can immediately process sensor data, communicating useful images to users rather than streams of raw data.
In recent years, the trend has been to put many of the intelligence-gathering sensors on unmanned vehicles, and now the trend is to use increasingly smaller unmanned vehicles such as UAVs. One option is to relay the raw sensor data to ground stations for processing. However, to be truly effective, these smaller sensor-based systems must be supported by a new generation of signal processing computers–powerful, rugged, and ultra-compact. Mercury Computer Systems' PowerBlock 50 computer, Figure 1 , was conceived as a way to meet this need, but the design challenges were significant.
Figure 1:The PowerBlock 50 computer was designed under some tight performance and environmental constraints
A small subset of the design goals helps to understand the scope of these challenges.
- Weight of less than 10 lbs: A range of weights could have been targeted. However, there is a class of tactical unmanned aerial vehicles with a total payload capacity ranging from 60 to 200 lb (27 to 90 kg). In a general sense, it is reasonable to allocate up to half of that payload capacity to computing, but not much more.
- Volume of less than one-half cubic foot: New generations of unmanned vehicles are not built to fit human dimensions. As with weight, a range of sizes could have been targeted. A one-half cubic foot system (15 cm3 ) will fit into many unmanned platforms. It is a volume target that current standard computer form factors are not able to meet.
- Maximum processing power; no fewer than 100 GFLOPS: Imaging systems can certainly be implemented with less than 100 GFLOPS of processing power, but image-exploitation algorithms, such as change detection, geo-registration, or automatic target recognition, demand at least that level of processing.
- High-speed, inter-processor communication infrastructure: In distributed-processing applications, the need for a deterministic high-speed inter-processor communications fabric is paramount. Such a communications infrastructure must be scalable for varying system configurations, support any-to-any simultaneous full-duplex data flow, and provide the performance and reliability defense applications demand.
- Ability to function in extremely harsh environments: Despite their technical sophistication, defense electronics systems must deliver uncompromised performance under difficult environmental conditions, including excessive heat, humidity, poor air quality, high altitude, shock, and vibration. Embedded computers must be able to keep their electronics from overheating, even when temperatures range up to 55?°
C and the air is too thin to be used for cooling. At the same time, they must possess the enhanced mechanical integrity to withstand high-shock and vibration forces at various frequencies.
The PowerBlock 50 design team recognized that current form factors for defense and aerospace computing platforms (such as 6U or 3U) would neither meet the weight nor volume targets which this project set out to achieve. At the same time, to effectively address a variety of processing-intensive applications, the platform needed to be configurable to support multiple processing engines with diverse capabilities. Ultimately, a multi-slot ultra-compact chassis specification was developed that, at roughly 4″ x 5″ x 6″ (10 x 13 x 15 cm), would adequately address the space-constraints of UAVs and other small platforms.
The next challenge was cooling the system. Functioning in extremely harsh environments means a tightly enclosed system chassis, while any processing elements delivering 100 GFLOPS of processing power are also going to generate significant amounts of heat. The design of the PowerBlock 50 had to incorporate the most effective means possible to dissipate heat in its confined space.
Conduction-cooling and spray-cooling were two potential options for removing heat from the individual processor modules. Because the overall system and module design was already constrained to a small size, conduction-cooling provided an efficient means to draw heat outward to the chassis, without the spatial requirements or mechanical complexities introduced by nozzles or pumps.
Furthermore, using a wedge-locking mechanism between processor, aluminum heat sink, and side walls of the chassis would ensure maximum heat conductivity, with the positive side-effect of increasing reliability across a range of environmental conditions (including shock, vibration, and temperature changes).
The final step in dealing with heat dissipation was to remove the heat generated by multiple processor modules from the chassis. The choice here was to use flow-thru liquid side-walls because the thermal capacity of a liquid is much greater than that of air. In addition, unlike air, the cooling capacity of a liquid is unaffected by altitude.
This approach does put the final cooling burden on the platform, to supply the liquid flow to take away the heat, but many platforms already support some form of liquid-cooled electronics. Almost any liquid can be used, provided the liquid temperature and flow rate are sufficient. Platform cooling strategies can also be very creative, such as platforms which use their own fuel, moving from storage tank to engine, to cool electronics.
To deliver maximum computing power within the defined size and cooling envelope, the design team had to select a number of slots for the chassis that would both provide an adequate power budget for processor and FPGA designs, and enough slots that the total processing performance of the system would exceed the 100 GFLOPS objective. The team selected a computational fluid dynamics (CFD) software package and used it to analyze the thermal performance of several designs, before finally choosing a six-slot chassis design, Figure 2 .
Figure 2:The unit shown with its cover removed
This design accommodates small processing modules with power budgets up to 60 watts, appropriate for FPGA, PowerPC, and x86 processing architectures with associated peripherals, making the PowerBlock 50 a modular and, therefore, customizable processing platform.
As its high-speed communications fabric, the PowerBlock 50 design team integrated a PCI Express switched backplane, providing four lanes of simultaneous point-to-point full-duplex communication to each of the six processing modules. With an aggregate bandwidth of 10 GBytes/sec raw data between processing cards and the reliability and maturity of an industry standard communications infrastructure, the PCI Express fabric makes the PowerBlock 50 an effective platform for distributed computing and provides a deterministic data path separate from Ethernet for high-speed inter-processor communications. It also ensures the overall architecture of the product is processor independent, so that any device which supports PCI Express can be considered for inclusion in future product designs.
Given this defined power budget, the designers next sought the processor, or processors, with the best possible GFLOPS/watt characteristics. Maximizing this ratio ensured that the selected device could handle the floating-point math essential to signal-processing algorithms and that the complete processing modules could be adequately cooled.
After evaluating dozens of processors, the team selected as its first candidate the P.A. Semi PA6T-1682M PWRficient processor, a dual-core AltiVec-enabled PowerPC vector processing engine, Figure 3 .
Figure 3: A board for the PowerBlock 50 computer using the P.A. Semi processor
Since then, PowerBlock 50 has evolved to support a growing variety of processors and configurations, including Xilinx Virtex-4 FPGAs (Figure 4 ), Freescale PowerQUICC III processors, with graphics processing units and next-generation Intel processors and chipsets soon to come.
Figure 4: A board with the Xilinx FPGA, for the PowerBlock 50 computer
This offers a roadmap for increased processing capability in the months and years ahead. By integrating a SATA carrier module that supports standard laptop-sized storage drives, the PowerBlock 50 can currently provide up to 128 GB of solid-state storage capacity, and will continue to advance with solid-state technology to support greater volumes of data.
For further configuration flexibility, each processing module is fitted with a customizable daughter card that brings I/O signals to front-panel external connectors via an internal flex-circuit interconnect. The system's initial I/O daughter card supports Gigabit Ethernet and RS-232 links. By re-spinning this simply designed daughter card, the PowerBlock 50 can be customized to bring in an abundance of industry-standard and proprietary interface protocols to address a wide variety of signal processing applications. v
Design goals exceeded
The final result is a system that exceeded the design goals listed above. A fully configured PowerBlock 50 weighs just below 7 lb (3.2 kg) and measures only 4.1″ x 5.3″ x 5.8″ (105 mm x 134 mm x 148 mm). It can be held comfortably in one hand. Configured with six high-performance PWRficient vector-processing modules, it delivers 192 GFLOPS of processing power and is fully capable of dissipating the heat generated by those modules. Rugged features include o-ring sealing for pressure, humidity, and EMI isolation, high-reliability connectors, extended temperature ranges, and locking modules for shock and vibration immunity.
The system is available now as the PowerBlock 50 EDK (Engineering Development Kit), a complete software development platform. The EDK includes a PowerBlock 50 system, Linux BSP development environment, and a desktop heat-rejection unit (HRU) to support the PowerBlock 50's cooling requirements. The PowerBlock 50 EDK is designed for desktop use in a laboratory or software development environments, focused on the development and optimization of run-time software deployable on PowerBlock 50 systems.
About the author
Thomas Roberts is a product marketing manager at Mercury Computer Systems, Inc. (www.mc.com), Chelmsford, MA.
Previous Extreme Design article
1. “Mars lander's chem lab is NASA's MECA,” EETimes , February 22, 2008
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