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Failures in Aerospace Applications, Part 2

Part 1 of this blog series introduces the main relevant failures that can occur in aerospace applications due to the heavy radiation environment, where the silicon-based ICs have to operate, known as SEEs (single event errors):

  • SEL (single event latchup)
  • SEU (single event upset)
  • SET (single event transient)
  • SEB (single event burnout)
  • SEFI (single event functional interrupt)
  • SEGR (single event gate rupture)

Let’s describe now in details the most common type of SEE: SEL (single event latchup).

This effect may be present on linear and logic components and may be destructive. SEL induces a failure known as latchup — that is, an activation of the parasitic bipolar transistors that are present in many widely diffused technologies, as in CMOS. The intrinsic bipolar transistors may start conducting, due to the presence of charges created by the radiation sources that cross the material, creating an abnormal behavior of the IC and sometimes the disruption of the device, in the case of activation of an avalanche mechanism.

Just to be more precise, in the CMOS technologies, by design, there is a parasitic structure in the circuit: the thyristor, a PNPN intrinsic structure constituted by two parasitic bipolar transistors, as in Figure 1:

Figure 1

The mechanism of the SEL.

The mechanism of the SEL.

The two parasitic transistors of the thyristor are maintained by an intermediate voltage that depends on many technology factors, including the resistivity of the epitaxy and/or the substrate, as in Figure 2:

Figure 2

The activation of the parasitic thyristor PNPN structure in CMOS technology by means of radiation sources.

The activation of the parasitic thyristor PNPN structure
in CMOS technology by means of radiation sources.

When a heavy ion or a proton goes through this structure, the radiation source generates e /p + (electron/hole) couples, which will generate a current into the substrate causing an increase of the intermediate voltage, Vi. As Vi reaches a sufficient level, the parasitic npn transistor, Q2, will be turned on, hence a current will flow through the Rwell area, and also the pnp parasitic transistor, Q1, will be turned on (see Figure 2). A parasitic current will flow between the voltage source VDD and the ground GND, and this current will be the sum of the currents flowing in the two parasitic transistors. Hence a latchup will occur.

A proper design of the IC’s layout can help in avoiding the dangerous effects of a latchup event by providing a safe path for the excess electrical current and preventing, at the same time, the avalanche issues.

To ensure that the designed device for a rad-hard (radiation hardened) application is not affected by latchup issues, there is a testing specification to check for the presence of a latchup — the eia/jesd78 ic latchup test.

What’s your experience with SEL? Do you agree on the need of a good design of the layout of devices for rad-hard applications, to avoid SEL or at least to limit this failure, with the goal of not affecting the functionality and the integrity of the IC exposed to radiations? Have you experience with the eia/jesd78 IC latchup test procedure, as specified by JEDEC?

16 comments on “Failures in Aerospace Applications, Part 2

  1. eafpres
    March 22, 2014

    @Paolo–this is outside of my experience, but I'm interested in the design rules.  Are there significant tradeoffs?  Now we have NASA sending smartphones into space; the consumer level chipsets are high density and high performance but surely not designed to avoid the failures you describe.  There is also a big push for military to use COTS (Commercial Off The Shelf).  I've heard that they take regular devices like a board level computer and put them inside another enclosure to make the suitable for use.

    Does the proper design for rad-hard anti-latchup reduce the density or speed of the chipsets?

  2. etnapowers
    March 23, 2014

    Hi Blaine, really nice question, the design rules to avoid latch up are commonly applied to all the types of devices, rad hard included. The only difference is that the activation of the thyristor in the aerospace environment may happen for SEL, to protect the device the common strategy is a screen provided by the radiation hard package of the IC.

  3. RedDerek
    March 23, 2014

    One semiconductor company actually takes advantage of the SEL condition to drive the output of the IC. This way a large current can flow through the output. The latchup is then released by intentionally shutting down the power for the next output to be driven. It took the output structure from 50ma capability to around 300ma capability. Wish I could mention the company and part, but that, unfortunately, is still proprietary as far as I would be concerned. A quick look at the company's site does not mention the IC, but it may still be on the custom side.

  4. etnapowers
    March 24, 2014

    @RedDerek: nice post, thank you for the informations. It's really a very interesting idea: inducing a SEL to increase the current drive capability, I think that the only shortcoming might be the reliability of the IC that have SEL , because this mechanism could damage the internal structure of the IC itself , especially for a long term usage.

  5. RedDerek
    March 24, 2014

    True it could damage the IC. The key is the specifications – limiting duration and current to keep reliability high.

  6. Netcrawl
    March 25, 2014

    @RedDerek  I agree with you it true it can damage ICs but we can prevent the occurence of latchup, latchup prevention in most commercial IC products can be achieved by adding the guard rings in I/O cells and placing the well pickups in internal circuits. 

  7. etnapowers
    March 26, 2014

    @Netcrawl: nice post, you're correct, the latch up is commonly prevented by mean of special design solutions and usually it is checked with special test procedures.

  8. chirshadblog
    March 27, 2014

    True but also it needs to be tested on a constant basis to make sure everything is matched.   

  9. etnapowers
    March 27, 2014

    Agreed, the reliability is the primary goal in this type of application, I guess the electrical qualification of this intentional SEL has been really an important step for the company which utilizes this solution.

  10. etnapowers
    March 27, 2014

    That's correct , this test has to be sistematically inserted in a test plan to ensure that the reliability requirements are satisfied.

  11. chirshadblog
    March 27, 2014

    @etnapowers: Indeed and each and every single object needs to be tested properly and also it is a must to document everything.               

  12. chirshadblog
    March 27, 2014

    @etnapowers: Reliability can be maintained as long as its being properly checked. Testing has to be done periodically in a much more methodical manner. You simply cannot stop testing once the product has been thrown towards the market. 

  13. Sachin
    March 31, 2014

    Single event latch-up is not entirely a negative thing and it is interesting to note that there are ways in which it can actually be harnessed to provide additional power that could be directed to other uses. The real challenge however is to ensure that this additional current is directed away from the IC as soon as it is created before it can do any damage to the IC itself and compromise its functionality or its efficiency.

  14. SunitaT
    March 31, 2014

    Generally, its followed by most of the companies to not to follow up with the performance of the product once its out to the market. Which might be taxing to the companies in the long run. By keeping tab on the perfomance of the product regularly, it can aid in proper maintenance. Apparently, testing is a must along with appropriate documentation on regular basis in a systematic way to ensure proper functioning of the product.

     

     

  15. SunitaT
    March 31, 2014

    Single event latchup is more common than most people think and can occur in many different IC circuits. However, since most of these circuits are not tested for SEL, it is often easy to overlook its significance. However, when it comes to aerospace applications, the effects of an SEL could prove fatal and therefore the reliability of the chips is of the outmost importance. This reliability can only be established through regular, intensive latchup testing.

  16. yalanand
    April 30, 2014

    The fact that this single event latch up may be present on linear and logic components is a disadvantage in that it can be destructive. This in turn incurs a lot of costs to the purchaser as they might want to repair it once it's damaged. It is not cost effective. Another factor that you should put in mind is the fact that the transistors induce itself due to the presence of the charges created by the source and this will bring about a huge loss.

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