Part 1 of this blog series introduces the main relevant failures that can occur in aerospace applications due to the heavy radiation environment, where the silicon-based ICs have to operate, known as SEEs (single event errors):
- SEL (single event latchup)
- SEU (single event upset)
- SET (single event transient)
- SEB (single event burnout)
- SEFI (single event functional interrupt)
- SEGR (single event gate rupture)
Let’s describe now in details the most common type of SEE: SEL (single event latchup).
This effect may be present on linear and logic components and may be destructive. SEL induces a failure known as latchup — that is, an activation of the parasitic bipolar transistors that are present in many widely diffused technologies, as in CMOS. The intrinsic bipolar transistors may start conducting, due to the presence of charges created by the radiation sources that cross the material, creating an abnormal behavior of the IC and sometimes the disruption of the device, in the case of activation of an avalanche mechanism.
Just to be more precise, in the CMOS technologies, by design, there is a parasitic structure in the circuit: the thyristor, a PNPN intrinsic structure constituted by two parasitic bipolar transistors, as in Figure 1:
The two parasitic transistors of the thyristor are maintained by an intermediate voltage that depends on many technology factors, including the resistivity of the epitaxy and/or the substrate, as in Figure 2:
in CMOS technology by means of radiation sources.
When a heavy ion or a proton goes through this structure, the radiation source generates e – /p + (electron/hole) couples, which will generate a current into the substrate causing an increase of the intermediate voltage, Vi. As Vi reaches a sufficient level, the parasitic npn transistor, Q2, will be turned on, hence a current will flow through the Rwell area, and also the pnp parasitic transistor, Q1, will be turned on (see Figure 2). A parasitic current will flow between the voltage source VDD and the ground GND, and this current will be the sum of the currents flowing in the two parasitic transistors. Hence a latchup will occur.
A proper design of the IC’s layout can help in avoiding the dangerous effects of a latchup event by providing a safe path for the excess electrical current and preventing, at the same time, the avalanche issues.
To ensure that the designed device for a rad-hard (radiation hardened) application is not affected by latchup issues, there is a testing specification to check for the presence of a latchup — the eia/jesd78 ic latchup test.
What’s your experience with SEL? Do you agree on the need of a good design of the layout of devices for rad-hard applications, to avoid SEL or at least to limit this failure, with the goal of not affecting the functionality and the integrity of the IC exposed to radiations? Have you experience with the eia/jesd78 IC latchup test procedure, as specified by JEDEC?