The previous blogs of this series describe the possible failures in aerospace applications:
- Single-event latchup (SEL)
- Single-event upset (SEU)
- Single-event transient (SET)
- Single-event burnout (SEB)
- Single-event functional interrupt (SEFI)
- Single-event gate rupture (SEGR)
In part 2, I analyzed SELs in detail. SEUs were described in part 3. Let's continue to analyze the possible failures in aerospace applications by focusing in this blog on SETs, SEBs, and, finally, SEFIs.
This failure is caused by transient noises on supply signals due to the radiation impact on the application board. The noise spikes can trigger the threshold of the internal comparators and generate a loss of functionality. Moreover, SETs can cause a serious issue for block system architectures. The error can be propagated in all the circuitry and even amplified by gain amplifiers present in the loop. The subsequent circuitry has to be properly screened to avoid this propagation of the error (see below).
Due to its intrinsic nature, the SET strongly depends on the bias point of the IC. Therefore, choosing the best bias point (in terms of spikes, noise rejection, linearity, gain, etc.) might help avoid these errors, especially if this choice is supported by a proper estimation of the worst-case scenario — the highest level of noise that may occur on the supply signal — and an effective filtering setup.
This failure is quite similar to SELs (which we discussed in part 2). The pairs electron/hole, created by radiation sources (proton/heavy ion) inside the silicon material, determine an increase in internal voltage in order to activate a parasitic intrinsic transistor, such as the parasitic bipolar transistor inside a power MOSFET transistor (see below).
(Source: ESA Microelectronics)
This error is destructive, so it has to be absolutely avoided. This can be done by a good design process. In the case of the CMOS power switch, a good design will make sure that the parasitic bipolar transistor cannot turn on and present an avalanche effect.
Single-event functional interrupt
JEDEC defines this as “a soft error that causes the component to reset, lock-up, or otherwise malfunction in a detectable way, but does not require power cycling of the device (off and back on) to restore operability, unlike single-event latch-up (SEL), or result in permanent damage as in single event burnout (SEB).” This type of error is “often associated with an upset in a control bit or register.”
A SEFI event is often related to an SEU. This failure can occur in integrated memories for aerospace applications, due to the inducted current caused by the presence of radiation sources in the aerospace environment (as we discussed in part 3). This loss of functionality, which often occurs in microcontrollers, impacts the content of the internal register.
In all applications requiring an integrated microcontroller, the SEFI can be really a big issue. Many times it is really hard to find. A testing methodology that can be implemented to check for the presence of SEFI is the functional testing shown below.
(Source: NASA archive)
In your opinion, what is the most dangerous of the three SEE failures presented in this blog? Which one is the most difficult to reveal and solve? Have you ever experienced an SET, SEB, or SEFI?