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Failures in Aerospace Applications, Part 4

The previous blogs of this series describe the possible failures in aerospace applications:

  • Single-event latchup (SEL)
  • Single-event upset (SEU)
  • Single-event transient (SET)
  • Single-event burnout (SEB)
  • Single-event functional interrupt (SEFI)
  • Single-event gate rupture (SEGR)

In part 2, I analyzed SELs in detail. SEUs were described in part 3. Let's continue to analyze the possible failures in aerospace applications by focusing in this blog on SETs, SEBs, and, finally, SEFIs.

Single-event transients
This failure is caused by transient noises on supply signals due to the radiation impact on the application board. The noise spikes can trigger the threshold of the internal comparators and generate a loss of functionality. Moreover, SETs can cause a serious issue for block system architectures. The error can be propagated in all the circuitry and even amplified by gain amplifiers present in the loop. The subsequent circuitry has to be properly screened to avoid this propagation of the error (see below).

Figure 1

(a) The SET, defined as 'a temporary disruption to the output of a device (transistor) or circuit caused by an ionizing particle passing through the device.' (b) The SET propagation mechanism from input to output.(Source: NASA)

(a) The SET, defined as “a temporary disruption to the output of a device (transistor) or circuit caused by an ionizing particle passing through the device.” (b) The SET propagation mechanism from input to output.
(Source: NASA)

Due to its intrinsic nature, the SET strongly depends on the bias point of the IC. Therefore, choosing the best bias point (in terms of spikes, noise rejection, linearity, gain, etc.) might help avoid these errors, especially if this choice is supported by a proper estimation of the worst-case scenario — the highest level of noise that may occur on the supply signal — and an effective filtering setup.

Single-event burnout
This failure is quite similar to SELs (which we discussed in part 2). The pairs electron/hole, created by radiation sources (proton/heavy ion) inside the silicon material, determine an increase in internal voltage in order to activate a parasitic intrinsic transistor, such as the parasitic bipolar transistor inside a power MOSFET transistor (see below).

Figure 2

The SEB mechanism.(Source: ESA Microelectronics)

The SEB mechanism.
(Source: ESA Microelectronics)

This error is destructive, so it has to be absolutely avoided. This can be done by a good design process. In the case of the CMOS power switch, a good design will make sure that the parasitic bipolar transistor cannot turn on and present an avalanche effect.

Single-event functional interrupt
JEDEC defines this as “a soft error that causes the component to reset, lock-up, or otherwise malfunction in a detectable way, but does not require power cycling of the device (off and back on) to restore operability, unlike single-event latch-up (SEL), or result in permanent damage as in single event burnout (SEB).” This type of error is “often associated with an upset in a control bit or register.”

A SEFI event is often related to an SEU. This failure can occur in integrated memories for aerospace applications, due to the inducted current caused by the presence of radiation sources in the aerospace environment (as we discussed in part 3). This loss of functionality, which often occurs in microcontrollers, impacts the content of the internal register.

In all applications requiring an integrated microcontroller, the SEFI can be really a big issue. Many times it is really hard to find. A testing methodology that can be implemented to check for the presence of SEFI is the functional testing shown below.

Figure 3

The testing method to reveal the presence of SEFI.(Source: NASA archive)

The testing method to reveal the presence of SEFI.
(Source: NASA archive)

In your opinion, what is the most dangerous of the three SEE failures presented in this blog? Which one is the most difficult to reveal and solve? Have you ever experienced an SET, SEB, or SEFI?

13 comments on “Failures in Aerospace Applications, Part 4

  1. Davidled
    April 5, 2014

    Circuit reliability would be improved by any advanced architectures. For circuit case, balance circuit could avoid any abnormal behavior due to single-event trigger, as shown in (b) of figure 1. I wonder if this single event would be occurred by Engine compartment near both right and left wing, because two engines generate a high noise and frequency.  Catastrophic failure could be minimized in the system level as adding fault-tolerant design process.

  2. etnapowers
    April 7, 2014

    @DaeJ: for sure this event would occur because of the presence of noise generator engines. This noise however is predictable in a specific part of the circuit , in this case the wings as you correctly said. The input noise due to the radiation is not predictable exactly, so a worst case scenario has to be simulated, and a specific protection circuitry can avoid a system failure.

  3. etnapowers
    April 7, 2014

    A good choice of the polarization point can avoid the noise propagation , hence the protection of the parts responsible for the setting of the biasing is extremely important to ensure the overall reliability of the system.

  4. etnapowers
    April 7, 2014

    One possible solution to avoid SEB is to provide a path to the current in case of activation of the parasitic  intrinsic transistor. This solution can be accomplished  by  a good design strategy of the IC for aerospace applications.

  5. samicksha
    April 7, 2014

    I often get confused in understanding which one is better to survive, SEFI causes the component to reset but does not require power off & on to restore, unlike SEL, or result in permanent damage as in SEB.

  6. etnapowers
    April 7, 2014

    SEFI, SEL and SEB are different types of failures caused by the same  cause: the radiation. The radiation fluence is not predictable and so the damages on the circuitry of the aerospace module might be dangerous in the same way

  7. etnapowers
    April 7, 2014

    Sometimes a functional failure may be more dangerous than a destructive failure, because the first failure might concern a data set containing for example an important recovery procedure and , the destructive failure might involve a part of the circuitry that is replaceble and hence the failure could be recovered.

  8. Davidled
    April 7, 2014

    It sound like trial-error method could be used to get a good choice of the polarization. Also, it is suggested that there are a filtering scheme with noise attenuation in order to minimize the noise propagation as absorbing all noise to the ground.  

  9. samicksha
    April 8, 2014

    When we talk of SEFI,  both the inherent device and process capabilities need to be taken into account along with the user design, i.e. design keeps important role in the entire picture.

  10. etnapowers
    April 8, 2014

    @DaeJ: that's correct, simulating the noise rejection through the IC may help to choose a good solution to avoid the propagation of noise introduced by radiations. The positioning of the filters has to be perfomed by taking into consideration the possible access points of the radiation noise.

  11. etnapowers
    April 8, 2014

    Agreed, the designer has to individuate the registers that may fail and the impact of this failure on the overall application circuit, by thinking to a procedure to detect and to recovery SEFI.

  12. samicksha
    April 9, 2014

    To add on, as mentioned in blog it is often induced from SEU.

  13. Sachin
    April 12, 2014

    It is clearly obvious that any highly developed architecture will improve reliability which is a very important factor in aerospace application. I think two engines will generate a lot of noise and high frequency and this can be predictable at some circuit point. @DaeJ I agree with the opinion that, the input noise due to radiation cannot be predicted but can be reduced by including fault tolerant design process in the system level.

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