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Fast-sampling analog front-ends: COTS or custom?

The first commercial off-the-shelf (COTS) analog front-ends (AFEs) designed for low bandwidth one-channel sensors showed what analog-to-digital integration can do. Then, COTS AFEs for applications like ultrasound imaging proved how matching multiple input channels improves performance. Now, radar, 5G, and other applications demand much higher sample rates with optimized, matched channels, and that’s changing the AFE landscape.

Higher sample rates on ADCs and DACs are just one of the changes. Zero-IF or direct sampling architectures are also gaining momentum. Next, modulation is moving from analog to digital domain, and AFEs are integrating tightly with digital processing. Here, at this design crossroads, can COTS parts offer enough flexibility to win in a range of designs, or will custom AFE designs using analog IP blocks take over at the high-end? Let’s take a quick look at some entries in the fast-sampling AFE race.

COTS AFE solutions for radar

Automotive radar chipsets have drawn intense interest, especially in self-driving scenarios. Many design teams settled on frequency-modulated continuous wave (FMCW) designs, simplifying chipsets where wide temperature range and cost are important considerations.

TI has built a portfolio of FMCW parts, starting with the second-generation AWR2243 radar AFE (Figure 1). It combines four receivers with three transmitters operating at 76-81 GHz and enables chip-to-chip synchronization for expanding channels. Its 45 MSPS sampling rate handles an IF bandwidth of 20 MHz for improved detection. This block integrates with processor and DSP cores in the single-chip AWR1843 radar processor, at 25 MSPS and 10 MHz IF bandwidth.

Figure 1 The AWR2243 radar AFE features chip-to-chip synchronization for expanding channels. Source: Texas Instruments

In defense and aerospace applications, raw performance usually dominates, and radar signal processing is often proprietary. As numbers of phased array elements increase and complexity shifts into the digital domain, a flexible AFE with programmable features can fit. Here, RF front-end chips can help configure specific radar frequency ranges.

ADI has launched a software-defined platform for phased array processing with its mixed-signal front-end, or MxFE. The AD99082 MxFE provides two 12-bit, 6 GSPS ADCs and four 16-bit, 12 GSPS DACs (Figure 2). It offers digital down-conversion and programmable finite impulse response (FIR) filtering along with delay adjustment on the ADC side, and digital up-conversion on the DAC side, all bypassable if desired. Moreover, multi-chip synchronization allows channel scaling for larger arrays.

Figure 2 The AD99082 analog front-end features multi-chip synchronization to enable channel scaling for larger arrays. Source: Analog Devices Inc.

GSPS IP blocks for SoC optimization

Many designers have been creating highly-optimized custom chips using the exact digital IP blocks they need, saving power and space. So, until recently, designers of applications like 5G and radar have had to choose standalone ADCs and DACs with GSPS rates. Now, a crop of GSPS ADC and DAC IP blocks is appearing, enabling custom chip designs with similar optimization.

Alphacore has a wide range of ADC and DAC IP blocks on various process nodes down to GF 22 nm. Its 10-bit ADC in 28 nm node runs at 2.4 GSPS using just 6 mW, while an 8-bit ADC in GF 22 nm node runs at 40 GSPS on 194 mW. A 12-bit DAC in GF 22 nm node runs at 6 GSPS using 121 mW.

Omni Design offers high sample rate ADC IP blocks implemented in its SWIFT op-amp based architecture for improved power consumption, down to 28-nm nodes. Its 14-bit ADC runs at 1.2 GSPS, and a 12-bit ADC runs at 6 GSPS. Omni Design’s DAC IP blocks run up to 18 GSPS.

Synopsys also has fast analog blocks, notably a 12-bit ADC with 3 GSPS rates in IQ mode, and a 12-bit DAC with 4 GSPS rates. The company has published some of the challenges awaiting designers using high sample rate in a blog post titled Very High-Speed Data Converters for 5G Analog Front-End.

 

Figure 3 The block diagram of MIMO radar SoC receiver highlights IP-centric innovation at the system level. Source: Unhder

Using IP blocks like these opens innovation at the system level. An excellent example is what Unhder created: a 192 virtual receiver GMSK code-domain MIMO radar at 77-79 GHz on a single chip for automotive applications (Figure 3). Each of the eight proprietary receiver blocks has two antenna inputs, one for azimuth and one for elevation, and a sophisticated cancellation feedback scheme. Receiver ADCs—no word on whose IP it is—run at 2 GSPS in a zero-IF architecture.

No such thing as generic AFE

It gets much harder for a merchant semiconductor vendor to offer an AFE meeting stringent performance requirements at the cutting edge of speed. Too much tuning for one application, and on top of that, the market is limited. Too many extra features are built in for flexibility, so designers may look for more optimized custom chips in the long run. Furthermore, merchant vendors have to prove out their standalone ADC and DAC technology first until AFE integration makes sense.

The challenge with either approach is matching converter performance across channels. Time-interleaving several ADCs is crucial, for instance. Take the example of ADX technology from Teledyne SP Devices, which offers digital post-processing to estimate and suppress mismatch error between ADCs.

For now, I’d guess the pendulum swings in the direction of GSPS analog IP blocks in custom chip designs until these high sample rates become common and application profiles emerge making off-the-shelf GSPS AFEs economically viable. Tighter digital integration also favors the analog IP block approach. It’ll be an interesting space to watch.

After spending a decade in missile guidance systems at General Dynamics, Don Dingee became an evangelist for VMEbus and single-board computer technology at Motorola. He writes about sensors, ADCs/DACs, and signal processing for Planet Analog.

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