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Field Programmable Analog – Technical Restraints, Part 1

Before we examine the merits of various programmable options for analog circuits we need to first examine the impact of field programmability on digital circuits.

Field programmable gate arrays, or FPGAs, are great. I should know. I’ve been using them since the late 80s. I’ve always said that the only problem with FPGA technology is that it is slow, noisy, power hungry, and, compared to ASIC implementations, it is very expensive. With problems like these, it is a wonder anyone would ever use an FPGA. And still, many people do.

The idea behind an FPGA was, as its name implies, to take gate array digital technology and make it field programmable. The FPGA’s programmable interconnects are the source of the problems. An FPGA achieves programmable interconnections by introducing active switches in the routing fabric. These active switches (transistors) consume power, slow down the circuit, introduce noise into the routing, and make the IC die larger and more costly. Therefore, the FPGA is always slower, noisier, requires more power, and costs a lot more than the same circuit implemented as a standard cell ASIC at the same process node.

At any given semiconductor process geometry, an FPGA can easily be up to 10 times worse than an ASIC when considering speed, noise, power, and cost. Again, if that is the case, then why would anyone ever use an FPGA?

When FPGAs were first introduced, this gigantic performance gap was indeed the issue. If you were considering an FPGA versus a standard cell ASIC, you had to be willing to accept serious compromises in performance in exchange for the field-programmability of an FPGA. FPGAs overcame a lot of these deficiencies by a relentless pursuit of Moore’s Law. Over time, the FPGA companies migrated to ever smaller process geometries to speed up the circuit, reduce power consumption, and reduce cost by reducing die size. An FPGA fabricated at deep submicron (DSM) geometries of say 65nm or smaller can compare favorably to a standard cell ASIC fabricated at 180nm.

Today, there are still many designs that need less than 150K ASIC gate equivalents, with the designs clocking at speeds slower than 100MHz. The speed and gate count specs of these designs can easily be satisfied by 180nm ASIC solutions. Modern digital FPGAs, fabricated at 65nm or smaller, are a viable alternative to 180nm ASICs.

By choosing an FPGA, a designer can forego the investment in ASIC design tools and IT infrastructure, eliminate the need for expensive semiconductor mask sets, bypass foundry prototyping lot charges, and avoid the need for expensive production test development hardware. For many industrial, defense, and medical applications, FPGAs are “good enough” and provide an attractive alternative to the large upfront investment required to design and fabricate a traditional ASIC.

FPGA companies spend tens of millions of dollars developing new FPGA platforms at DSM nodes. They amortize these costs across a marketplace of low- to medium-volume customers. This solution made lots of sense in the digital space. Is there an equivalent Moore’s Law scaling in the analog world? That is the question for which we need an answer.

In our next installment, we will explore just how programmable you should make your analog circuits. We will look at the differences between digital and analog, and we will see if Moore’s law can come to the rescue in analog, as it did in digital. Or maybe analog IC integration needs solutions other than just semiconductor scaling to meet design, performance, power, and cost goals.

3 comments on “Field Programmable Analog – Technical Restraints, Part 1

  1. eafpres
    February 22, 2013

    Hi Reid–I've been involved in projects trying to get custom ASICs and all the things you mention as up-front costs and back-end quantity commitments are real.  In your comparison of current FPGA vs. 180 nm ASICs, do you have a feel for the usage volume where things balance out, above which you should consider an ASIC?

  2. Brad Albing
    February 26, 2013

    I've been involved in some of these same issues too – front end costs, NRE, amortizing NRE over an uncertain number of unts over an uncertain amount of time…. It can become a gigantic headache.

  3. amrutah
    March 1, 2013

    FPGA's are good for initial testing of the logic and implementation, but if a product is to be targeted then a custom ASIC will be a good bet, as it will make the chip small and less no. of pins to handle.

      I cannot imagine of having a programmable Analog counterpart.  The FPA's have to have a good set of current sources, reference voltages, different supply voltage rails, very top notch spec for the no chip opamps.

    I am afraid we will end up having a lot of trims in case of Analog programmable chips…

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