Moore’s Law makes FPGAs a viable alternative for digital. Last time around, we showed that if you scale an FPGA design down to deep submicron (DSM) process nodes, an FPGA can become performance and cost competitive with 180nm ASIC solutions. In the digital world, transistor scaling delivers a lot of benefits. Scaled digital transistors are faster, lower power, and smaller than the same transistor function at a larger semiconductor process geometry.
The question is, does scaling transistors in an analog device make for a viable field programmable analog array?
In a field programmable device, transistors are used as switches to make the programmable interconnect. In a digital device, these switches contribute negatively by:
- Increasing the size of the circuit
- Reducing the noise margin
- Increasing power consumption
- Making the circuit run slower
- Making the whole thing cost more
Additionally, as digital circuits scaled to smaller process nodes, the gate oxide thickness is reduced, which requires a lower operating voltage. In digital this wasn’t necessarily a bad thing, because a lower operating voltage means lower power consumption; and, since digital uses ones and zeroes, switching such circuits could accommodate a reduced noise margin.
Analog don’t scale like digital, baby. Yes, I know that some analog circuits can certainly take advantage of transistor scaling. Take those 80GHz ADCs for example (that was a joke). In general, a large majority of analog circuits benefit from the higher operating voltages that can be found on “more mature” thick oxide process nodes. The proof of this can be found by looking at how many analog components from the major manufacturers are still fabricated on 0.35micron and 0.18micron process nodes.
High-performance and high-precision analog circuits benefit from higher operating voltages because many of the best analog circuit topologies require the stacking of transistors (think diodes). DSM nodes, with their lower operating voltages, reduce the number of transistors that can be stacked, due to the diode drops.
Size does matter. For analog, bigger is better for the vast majority of circuits.
Why can’t I use transistors for switches in my programmable analog array? Just as in digital, the only problem with using transistors as the programmable interconnect in an analog array is that these switches make the circuit noisy, change its impedance, slow things down, consume excessive power, and make it large and expensive.
In a digital circuit, the transistor that acted as a switch was connecting two digital devices. The driving circuit only needed to drive a one or zero, and the receiving circuit simply needed to detect that one or zero. The fabric transistors in a digital FPGA could be relatively small but with large resistance.
Many useful analog circuits cannot tolerate large resistances in signal paths. Adding these large resistances coupled with the capacitance inherent in these circuits severely limits speed and analog bandwidth of such circuits.
If field programmable analog is such a bad thing, is there no way to lower the cost and simplify the development of analog ASICs? FPGAs greatly simplified the design of digital ICs and significantly reduced their development costs. Field programmable analog is too much of a performance and price negative to be viable in the marketplace.
Configurable analog is as close to programmable analog as you want to get.
The patent office makes a distinction between programmable and configurable ASIC solutions. They see programmable technologies as solutions that use active transistor switching that can be programmed in “the field.” Configurable technologies utilize vias that can be configured in “the fab.”
Via configurable analog is a better way to reduce cost and simplify the development of analog ASICs. Vias are the interconnect element used to connect different metal layers of all analog and digital ICs. Compared to the active switching transistors of an FPGA, vias are tiny. In fact, compared to just about anything in an integrated circuit, vias are tiny. Vias are small squares or plugs of low resistance material that goes between metal layers in all semiconductor devices.
A via configurable array consists of silicon-proven analog and digital resources that are overlaid with a global routing fabric. Wafers containing these arrays can be partially processed and staged at the foundry awaiting configuration. A user’s design is configured onto the array by a single mask layer change that places vias between metal layers in the global routing fabric.
- Mask costs are amortized across many customers.
- No full-custom layout costs.
- It's low-risk because the underlying IP is well characterized and silicon-proven.
- Processing time at the foundry is a couple of days versus three months.
- Complete projects can go from kickoff to production-ready silicon in three to five months versus the 18 months typical of a fully custom development.
- Complete respins can be accomplished, fabricated, and packaged in under four weeks.
- Performance is excellent because the underlying IP is full-custom, spec-driven IP, and the interconnect uses standard metal and vias, not field programmable transistors.
In a nutshell, via configurable analog can reduce development cost and development time by 75 percent or more compared to traditional full-custom IC development. And via configurable mixed signal arrays have the performance and production costs that the market demands.
Today, companies in the defense, industrial, medical, consumer, and automotive markets are using via configurable mixed signal solutions in production volumes from hundreds to millions.