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FinFETs & Analog

At DAC this year, it was impossible to go to a vision talk, keynote, or other high-profile event without hearing about how FinFETs were going to save us and keep Moore's Law going for a little longer. At this point, I think most people have a vague idea about what FinFETs are, and we have all seen the cross-sectional diagrams of them. I found this picture in the archive for the third Fornel Nanelectronics Workshop. I found it helpful because it showed exactly why they are called multi-gate structures.

(Source: Texas Instruments)

(Source: Texas Instruments)

A panel at DAC discuseed FinFETs and analog design. Scott Herrin, an analog design engineer with Freescale Semiconductor, talked about the obvious changes that would come with FinFETs. He mentioned increased gain and reduced leakage as advantages and quantization as a negative. However, other panelists said that this would end up being a positive, because it would help with matching. One thing I heard from this panel and at a Synopsys lunch was that the parasitics associated with these devices are a little harder to extract. There are more of them, and analyzing them will be more difficult. Of course, the EDA industry will love it when we are even more dependent on them.

I thought I would try and dig into some of these issues a little more. What I found was lots of information that wanted to get deep into the physics of the devices, but few sources talked about the practical implications of these devices for an analog design engineer. At the same time, many people were comparing a 28nm planar process with a 14nm FinFET processes. That confuses the issue further, since 14nm contains a lot more complexity on its own — even if it were possible to produce planar transistors at this size. We need to separate out those issues. Let me start by looking at a couple of issues: short-channel effect and quantization.

In a planar transistor, you want strong capacitive coupling between the gate and the channel. Current that flows in the channel is good current, but you want to minimize the current that flows out of the channel. This is leakage, and it has been increasing with smaller device sizes, because controlling the channel has become more difficult. This is due to the decreasing oxide thickness and reduced mobility in the channel.

Decreasing mobility is a by-product of heavily doping the channel to reduce leakage. By increasing the coupling between the gate and channel, you could control the short-channel effects better and lower the drain-induced barrier lowering. This would give you a better ION to IOFF ratio for a fixed VDD . Reducing the leakage implies a very thin body. You could improve the coupling by having the gate on both sides of the body. This would reduce the short-channel effects. That is what a FinFET does.

That is the good news. Now for the bad news: FinFETs cannot be built in any arbitrary size. You basically cannot change the height or width of a fin; that is fixed in the production process. What you can change is the number of fins, but this happens in discrete increments. There are no half fins. It appears that two fins may be typical for some applications, though Intel always talks about three-finned devices.

It also appears that some effects in the manufacturing process lead to the two-finned approach. One thing I read said this is due to a self-aligned spacer process used to create tight pitch fins. Sacrificial spacer elements result in the creation of a pair of fins. This may be a problem for the creation of static memory, which relies on minimum feature sizes, but it may not be such a big issue for analog circuitry. As can be expected, much of the early analysis is being targeted at the digital community, which is stretching for the smaller nodes. The analog community in general is still quite happy being on much larger geometries.

It may be too early to tell how useful FinFETs are going to be for analog design. I will continue to look into this issue and report here on any interesting work I find. As an analog designer, how important do you think the quantization problem will be?

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4 comments on “FinFETs & Analog

  1. Scott Elder
    July 5, 2013

    Brian – I think simulation times will increase because today's single device will become a mutli-transistor composite device.  So where before one had a schematic with 16 transistors and one model to compute for each transistor, now one will have two levels of a schematic with each of the 16 transistors now having their own 16 transistor schematics.  A 16 model computation becomes a 256 model computation.

  2. eafpres
    July 8, 2013

    @Brian–per Scott's comment “now one will have two levels of a schematic with each of the 16 transistors now having their own 16 transistor schematics”

    You mention that 2-fin or 3-fin instances may be common.  Since these sum to form the “device level” effect, it seems to me you would have to add Monte Carlo simulation of the 3 fins to get the aggregate which would further lengthen run times.

    Perhaps if the process ranges are constant the Monte Carlo could be done ahead of time, and an aggregate solution used as the feature model in higher level design?

  3. BrianBailey
    July 8, 2013

    It is not clear to me how much variation can be expected in the fins. While the sizes of them are somewhat constrained by the fabrication processes, I dont know if we can expect less variation in them or not. An interesting question that is beyond my knowledge at this point.

  4. SunitaT
    July 29, 2013

    Scott Herrin, analog design engineer at Freescale Semiconductor, said in a Design Automation Conference panel on using FinFETs for analog circuits: “There are definitely things that I see and get enthusiastic by and there are also things that I get concerned about. The noticeable benefits are increased gain and reduced leakage. You do get the issue of quantized width.”

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