I have often spoken about the differences in the analog and digital flows and while the two pieces are designed and verified separately, it really doesn't amount to many difficulties.
The same is true when a small block of one is integrated into the other. But when large chips are being designed that contain significant portions of both, it can lead to a clash of cultures. One area where this becomes a real issue is with floorplanning . This has become an essential part of the digital flow which is primarily top-down, but not for the analog flow which is bottom-up.
Floorplanning is part of the physical implementation process where the physical location of instances, formation of chip and block boundaries, and pin placement is optimized. It may also have to take into account constraints related to power supply and signal distribution, system-level constraints such as chip size, aspect ratio, and I/O locations. If hard cores are included in the chip this will also place constraints on the floorplanning process.
Early in the chip design process, many aspects of the design are not yet known and so estimates are used. This enables budgets to be set and provides guidance to the design teams. As the design progresses, these estimates become more refined and it becomes possible to see if any new information would cause problems with the floorplan so that adjustments can be made in an incremental manner.
But how does this play into the analog flow? Analog implementation is more likely to place transistors and route wires in order to optimize the implementation and things such as pin placement and aspect ratio are usually not primary design considerations. But without consideration for the rest of the chip it may not be possible to create a device that finds an overall optimum layout. In this blog I am going to describe some of the primary considerations that are used in floorplanning and highlight the ways in which they impact the analog portions of the design.
Designs these days have multiple power domains and the routing of the power and ground planes impacts all parts of the chip. They must be routed so that they can deliver the necessary current within acceptable voltage degradation known as IR drop. Various topologies can be used such as trunks, rings, meshes or combinations of these. In many cases metal layers are reserved for their implementation. There may be considerable advantages to keeping blocks that use the same power domains in a close proximity to each other. Signal routing
The performance of most chips is limited by timing introduced by signal routing. The system architect can often identify the critical paths in the design and these are given priority in the floorplanning process. This is done by placing blocks, establishing block shapes, and placing pins so that these critical signals have the minimum length possible. After these are optimized any analog signals not considered critical are dealt with followed by the remaining digital data signals. For analog nets constraints may include matching parasitics, minimizing coupling effects, and IR drops. Routing resources
A certain amount of the chip surface is reserved for signal routing. This includes any shielding that may need to be provided for sensitive analog signals. Enough area must be reserved such that detailed routing does not run into congestion problems but at the same time does not waste chip area. In some cases, the digital blocks may enable routing through the block to help relieve congestion. This is rarely the case for analog blocks. Pin optimization
Pins are located to minimize routing lengths and parasitics. It will usually consider constraints placed by hard IP blocks first or any external constraints and then proceed in a top-down manner to determine the best placement for the other signals. Analog blocks can place constraints on the process if a bottom-up examination of the designs leads to placement that could impact the block implementation.
It should be remembered that the first floorplan is not cast in stone or even silicon. It provides guidance and acts as a vehicle to refine the constraints after various stages of implementation have been completed. It is hoped that iterations will follow a linear progression rather than each step taking on major changes as this can disrupt many of the other blocks in the chip.
Floorplanning is a necessary part of any mixed-signal design. Do you find it to be a big inconvenience in analog implementation?
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