Focus on precision timing challenges

Electronic clock devices are not your grandfather's chime clock; no, the clocks used in today's electronics are much more precise and versatile. Electronic clocks are the quarterback of the PCB team that determine the rhythm and accuracy of the signals getting passed around and off the board.

Output Timing Examples

Clocks are everywhere in electronics. They come in all shapes, sizes, and flavors. There are high-speed, low-speed, low-power, low skew, non PLL clock buffers, multiple outputs, single outputs, single voltages, multiple voltages, zero delay, programmable, non-programmable and clocks for every application including memory, telecom, datacom, printers, multimedia, and much more.

Hot times
What are the hot topics affecting these clock/timing designs? You wouldn't be wrong if you said the need for speed or faster rates is a hot topic, as is the need for dual clock generators, but what most customers are concerned about is enough to give you the shakes or jitters.

“The hottest topics in clock design are jitter performance and cost” said Jeffry Keip, Senior Product Marketing Manager for Clocks and Signal Synthesis Products for Analog Devices. “However, while features such as speed, synchronization and power are each important and may be particularly hot in specific applications, lower cost and better jitter are universal needs and are consistently in demand by customers,” he added. The first dedicated clock part to be offered by Analog Devices, is the AD9540, which will be ready for mass sampling by early May of this year. At less than $10 in thousand piece quantities, this part will enable customers to generate sub-picosecond jitter, and LVPECL level clock signals at up to 650 MHz.

Analog Devices AD9540 clock

“Because systems keep getting faster, jitter and skew are perennial hot topics for clocks,” agreed Bill Birch, Timing Solutions Design Manager for Freescale Semiconductor (a wholly owned subsidiary of Motorola). The company is also seeing increased interest in high-availability fault tolerant systems with redundant clock trees in computing and networking applications. “System margining capability (also called incremental frequency adjustments) is also gathering interest,” continued Mr. Birch. “Additionally, more customers are using differential clocking for local clocking as well as clock distribution. For memory applications there is a migration in clocking from SDRAM to DDR1 and is poised to move to DDR2,” he added.

Freescale has pioneered advanced clock generators, called Intelligent Dynamic Clock Switches (IDCS) to support sophisticated fail-over clock schemes. High-availability systems need this sophistication to prevent system crashes in the event of a failure of the primary clock source. Examples are the company's MPC9893, MPC9894, and MPC9993.

Freescale MPC9894 IDCS chip in BGA package

“For system margining, Freescale offers programmable synthesizers, such as the MPC9229 and the MPC9230 that allow incremental adjustments to the target frequency,” said Birch. “This allows users to analyze and position their systems for optimal reliability. To address future memory clocks, Freescale will begin sampling DDR2 clocks in May ” starting with the fully JEDEC compliant MPC96877.”

“Application specific jitter is a hot topic in clock designs,” according to Sam Limoun, Timing Solutions Marketing Manager for Pericom Semiconductor. “As timing margins get tighter the jitter spec gets smaller,” he observed. For example, the cycle-cycle jitter spec for Pericom's DDR266 is 75ps, and now the spec for DDR2 (533) is 40ps. Similarly, the jitter spec is getting tighter for PCI-Express and S-ATA clocks.

Pericom PCI-Express

“However, some applications like the PC motherboard are more affected by cycle-to-cycle jitter while others like communications need to be aware of long term jitter,” said Mr. Limoun. Cycle-to-cycle jitter is a deviation in clock output transitions from an ideal position. While long term jitter is the difference in a clock output transition from its ideal position over many cycles. To reduce jitter, Pericom uses a number of filtering and bypassing methods to eliminate ground bounce and reduce power supply noise, which are the two main causes of jitter.

Cypress Semiconductor also sees jitter as a very important issue but especially as SerDes designs move toward lower end applications. Cypress is focused on creating clock generators with jitter below 10ps and buffers with jitter below 1ps. The company also is pushing the speed of its clocks towards 1GHz.

For example, the CY2DP3110 from Cypress Semi is a low-skew, low propagation delay with a 2-to-10 differential fan out buffer. The device is implemented on silicon germanium technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 3.0 GHz.

Cypress Semi High-Frequency Programmable PECL Clock Generator

The requirements for clock designs really depends on the market it serves. For example, according to Sergis Mushell, Clock Product Line Strategic Marketing Manger for Exar, the hot topics for the PC market include the needs for a dual clock generator for the white box segment as well as high frequencies with low jitter requirements. “The development of new technologies in the PC market pushes clock designers to make flexible generators that include more PLLs in a system,” said Mushell. “The older systems needed 3 PLLs, however the newer ones require 4 PLLs,” he said.

The XRK4991 3.3/2.5V High-Speed Low-Voltage Programmable Skew Clock Buffer from Exar offers some powerful parts such as user selectable control over system clock functions. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances. Each output can be hardwired to one of nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. When combined with the internal PLL, these divide functions allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This capability minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility.

Exar Programmable Skew Clock

In the communications market, Mushell says there is a need for clocks that support multiple I/O standards such as low-voltage differential signaling (LVDS) and low-voltage positive emitter coupled logic (LVPECL); lower jitter clocks and lower propagation delay buffers, as well as devices which offer lower output skew in the device. Mushell also says new characteristics need to be developed in the comms market such as static phase offset, dynamic phase offset, and half-period jitter. The standards bodies such as JEDEC can help demonstrate the key performance issues.

“In the communications industry there is a trend towards convergence, where many functions and characteristics, such as computing, networking, storage, and security are increasingly found in a single platform,” said IDT's Sean Fan, Director of Marketing, for communications timing solutions and telecom products. This is possible because more advanced components are available, which are driven by demand by carriers to lower their operation expenditures, as well as the diversified needs of end-users for services.”

“As a result of this convergence,” continued Mr. Fan, “designers are looking for timing solutions to meet the new challenges from multiple domains. For example, many different frequencies with distinct specifications are needed for a board or a module. High reliability needs will require systems to support redundancy and that means that timing devices have to support multiple references and holdover functions.” You can expect IDT to address these needs with new products that offer more programmability and versatility.

Resolving the time
The emergence of new architectures in the communications industry is good because it's a response to customer needs. However, it's not free because it also challenges the timing circuitry.

In some new architectures the serial buses are beginning to replace traditional parallel schemes, and differential signaling is replacing single-ended signaling in parts of the system. Additionally, memory architectures are moving to DDR1 and soon to DDR2. Differential signaling is required on some processors and backplanes. These architectures require both types of clocks. Serial buses require low jitter, good frequency stability, and often high-speed differential clocks.

Freescale offers the MPC9850 QUICCclock configured to provide the processor and bus clocks, the differential RapidIO/LVDS clocks and the Ethernet clock ” all from a single crystal. In addition, Freescale offers a family of differential clock buffers with low jitter and exceptional frequency range in all of the standard I/O configurations including, PECL, LVDS, HSTL and SSTL.

“Designers working on new architectures to support multiple protocols need to re-think their traditional approach towards system timing design and implementation,” said IDT's Sean Fan. “If you treat advanced system timing as a simple, isolated device selection issue, and deal with it after major architectural decisions are made, you may find the approach does not work as elegantly as you would like,” he added.

IDT suggests designers evaluate their timing requirements, such as jitter parameters and skew budget, as early as possible in their overall system design process. “Timing is everything is a clich, but if you ignore it, timing issues can be major obstacles for time-to-market needs of any complex digital system,” observed Fan.

Exar's Mushell says a greater array of I/O clocks is needed to address the market place because there are very few standard products that can be used across all platforms. “Additionally, the evolving architectures, clock trees and new devices are needed to address the alphabet soup of different I/Os and voltages, and an increasingly segmented market with more stringent clock requirements,” he said.

Mushell says the rapid growth of the communications market has driven the implementation of more complex tree structures for clock distribution. “These clock trees are needed to feed the many nodes that designs require to move data through many different functional blocks with digital time domain precision,” he said.

Exar says it offers solutions that address the issues that the networking customers face everyday in their clocking tree. These solutions range from addressing the skew (Exar announced 18 different programmable skew clocks in March 2004), jitter, failsafe clocks (an intelligent clock switch), reducing propagation delay (zero delay buffers), and distribution of clocks where non-PLL devices are needed (fan-out buffers).

New architectures and new standards in the communications sector often bring new challenges with them, observed ADI's Keip. For example, “the SONET stratum clock specifications for optical networking (which are quite old) are most responsible for the growing need for redundant clock signals; for clock chips that can maintain outputs even when the reference disappears (“holdover”), and clocks that can compensate for phase differences between two or more redundant reference signals,” said Mr. Keip.

“As these needs emerge, clocking vendors must be flexible and innovative in their product definition and development,” says Keip. “Generically, the ongoing need for better signal-to-noise performance from data conversion products at ever increasing speeds is fomenting the need for extremely low jitter clock products.” Lab experiments with early versions of the AD9540, according to Keip, have demonstrated it is capable of RMS jitter performance below 500 fs when paired with relatively inexpensive off-the-shelf variable crystal oscillators.

Clock in with ASICs and FPGAs
Application Specific ICs (ASICs) and Field Programmable Grid Arrays (FPGAs) serve their specific markets and applications well, especially for the data path and control logics, says IDT's Sean Fan. In general, designers want to focus on functions implemented in ASIC/FPGA for schedule, debugging and testability. While it may seem convenient and cost effective, integrating extensive and high-performance timing functions into ASICs and FPGAs can be a challenging and a highly risky undertaking. IDT's approach is to offer standard timing devices that complement ASICs and FPGAs, and allow designers to stay focused on their value-added activities.

Processors, controllers, ASICs and FPGAs have have on-chip timing issues similar to board and system issues between chips. “However, because the timing between boards and chips is increasingly difficult, the need for clocks continues,” observed Bill Birch of Freescale (Motorola) Semiconductor. “In small systems, a single clock or crystal may be all that is required, but in large or multi-board systems and in systems that require redundancy, clock subsystems can get complex, requiring many clocks per system,” he said.

“The internal clocks on the ASICs (or processors) drive the external clock performance requirements,” pointed out Mr. Birch. “They determine many of the critical specifications such as duty cycle, jitter, frequency, I/O levels, and responsiveness or bandwidth. For example, the Freescale/Motorola PowerPC and PowerQUICC processors have specific requirements for the clock references.” Just as importantly, Freescale has a line of clocks that is compatible with the Freescale processors, most ASICs and FPGAs, and other processors.

Offering a similar point of view, ADI's Jeffry Keip says FPGAs and ASICs are not able to even approach the sub-picosecond jitter performance capability of the ADI AD9540. FPGA's and ASICs do, however, serve applications at the low end of the performance scale. “Companies likely to be affected by emergence of clock capability in ASICs and FPGAs will be those who are heavily invested in clocks for computer motherboards and consumer level products. However, incorporating clocks onto FPGAs and ASICs adds sufficient design risk such that ADI doesn't expect it will have a significant impact in any of the clock markets,” observed Mr Keip.

“PLLs in ASICs and FPGAs are targeted at addressing the needs of protocols such as Hypertransport, Rapid IO, Utpoia, and SPI that demand the clock to be sent along with the data for chip to chip communication,” said Mushell of Exar. Agreeing with others such as ADI, Mushell says, “The embedded PLLs within the FPGAs and ASICs today don't offer the economics, precision and the complexity that discrete timing devices have for distribution of clocks throughout the board.”

“The high cost of using ASIC or FPGA solutions would not justify using the available pins to implement clocking features,” noted Mushell. “Furthermore, the strong drivers that are needed to use clocks throughout the PCB are not available in the FPGAs and ASICs. In summation, the economics of incorporating the distribution of the system clock in the ASIC and FPGA is not there in many applications.”

Jittery Challenges
Reducing noise and jitter is a key design art for clocks. Clocks generally involve multiple outputs switching large loads. This switching energy plus other internal and external system noise on the power/ground/IO pins provide a significant jitter potential. However, there are other, not so obvious, sources of noise as well.

The overall design strategy at Freescale, according to Mr. Birch, is to deal with these less obvious sources. The company aims to minimize the on-chip noise the company products generate, and desensitize its clock to any sources of noise, either internal or external. Some of the design/layout techniques offered by Freescale include a long list such as differential signaling, special digital-analog interfaces, PLL isolation, output designs, power bus design and routing, on-chip LDO regulators, filters and filter design, PLL performance parameters, device orientation, transistor topology and type/package parasitics, transmission line considerations, pin assignments, number and placement of power, ground and output pins, crosstalk elimination and shielding.

“Different applications have different requirements with regards to the causes of jitter, its ramifications and even the methods in which to measure jitter,” says IDT's Sean Fan. “Understanding the performance goals of the end applications, such as standards compliance, is essential. In addition to providing general-purpose timing devices for a variety of applications, IDT offers application-specific timing solutions to meet the special challenges that customers encounter in their particular applications. For instance, the company's Stratum timing family targets communications systems that require stratum-level compliance.

The IDT82V3155 is an enhanced T1/E1/OC3 WAN PLL with dual reference inputs. It contains a digital phase-locked loop (DPLL), which generates a low jitter ST-BUS, 19.44 MHz and 155.52 MHz clocks, and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference. The IDT82V3155 can be used in synchronization and timing control for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse source. It also can be used in access switch, access routers, ATM edge switches, wireless base station controllers, or IADs (Integrated Access Devices), PBXs, line cards and SONET/SDH equipments.

IDT's SONET/SDH clock application

The ideal clock/timing device would offer zero jitter, zero delay and zero emissions. A fine balance between these three elements is required to ensure when addressing one attribute, the other areas are not adversely impacted. Designers may need to prioritize some of these parameters to provide an optimum solution which best addresses their system requirements.

There are many timing challenges getting your design to work most efficiently and fortunately, and unfortunately, there are many solutions. Here are some companies that can help you with your needs:

Company Contacts

Agere Systems
Tel: 1-800-372-2447 or 1-610-712-4323

Analog Devices, Inc.
Tel: 800-ANALOGD (800-262-5643)

Cypress Semiconductor Corp.
Tel: 408-943-2600

Exar Corp.
Tel: 510-668-7000

Integrated Device Technology (IDT)
Tel: 408-727-6116

Freescale Semiconductor (subsidiary of Motorola Inc.)
800-521-6274 or 480-768-2130

Pericom Semiconductor Corp.
Tel: 800-435-2336 or 408-435-0800

PMC-Sierra, Inc.
Tel: +1 (408) 239-8000

Silicon Laboratories, Inc.
Tel: Phone: 512.416.8500

0 comments on “Focus on precision timing challenges

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.