Advertisement

Article

Freebie PLL design tool debuts with PLL hardware

Norwood, Mass.—RF chip maker Analog Devices, Inc . (ADI) is rolling out a new generation of its existing ADIsimPLL PLL (phased-locked loop) circuit design and evaluation tool, as well as two new PLL synthesizers. As you might expect, ADI's free-of-charge ADIsimPLL has been downloaded more than 25,000 times since its introduction four years ago.

The company's latest ADIsimPLL v3.0 tool builds on previous versions of the software. As a dedicated PLL simulation package for the company's PLL frequency synthesizers, it helps you prototype designs and optimize them. Thankfully, ADIsimPLL v3.0 is compatible with files from earlier versions of ADIsimPLL.

ADIsimPLL v3.0 now offers nine new loop-filter topologies, a new VCO (voltage-controlled oscillator) reference library editor, and enhanced VCO libraries. It also includes new analysis features, as well as support for six new hardware devices.

PLL Silicon

On the hardware side, ADI introduces its ADF4156 and ADF4002 chips, providing low-frequency and high-frequency PLL approaches for a range of wireless base-station equipment. These devices can work in circuits for GSM, PCS, DCS, WiMAX, SuperCell 3G, CDMA , and W-CDMA networks.

The ADF4156 is a fractional-N PLL synthesizer operating at 6-GHz. ADI claims that's one of the industry's highest frequency of operation for a fractional-N device. The '4156 can implement LO s (local oscillators) in up-conversion and down-conversion sections of transceivers and transmitters.

The power-managed ADF4156, operable from 2.7-V to 3.3-V, comprises a low-noise PFD (digital phase frequency detector), a charge pump, and a programmable reference divider. An S-delta-based fractional interpolator supports programmable fractional-N division. The IC's RF-output phase is programmable for applications that require a particular phase relationship between the output and a reference.

The ADF4156 also features so-called cycle-slip reduction circuitry. It leads to faster PLL lock times, without the need for modifications to the PLL's loop filter. Finally, the ADF4156 is pin-compatible with ADI's predecessor ADF41xx family of synthesizers.

Lower-Frequency Counterpart

For its part, the ADF4002 operates at up to 350-MHz. At those frequencies it's useful to implement clock conditioning, clock generation, and IF (intermediate frequency) LO generation.

The '4002 consists of a low-noise digital PFD, a charge pump, and a programmable reference divider and programmable-N divider. The 14-bit reference counter accepts selectable frequencies at the PFD input. A complete synthesizer is implemented if the PLL is used with an external loop filter and VCO. Like the '4156, this IC has a power supply range of 2.7-V to 3.3-V.

The Software

The ADIsimPLL v3.0 tool improves the range of PLL loop filter topologies available within the simulator, from 9 to 18. Many of the nine new loop filter topologies include higher-order active filters; these can provide additional spurious rejection, particularly in fractional-N designs.

To assist in entering and maintaining VCO and reference oscillator data libraries, this latest version comes with a dedicated VCO/Reference Library File editor. As the name implies, it supports browsing through a VCO or reference oscillator library file, as well as user-entry of VCO tuning and phase-noise data.

In ADIsimPLL Version 3.0, the closed loop gain of a PLL is calculated and displayed on a FreqDomain page, while phase-noise plots have been enhanced to show the contributions from each of the noise sources in the PLL.

The new version also comes with an expanded VCO/VCXO (voltage-controlled crystal oscillator) library collection. It will automatically search for suitable VCOs that meet your frequency requirements.

Other features include automated design of output matching circuits for ADI's ADF4360-8 , and modeling of dither effects of fractional-N designs.

Price And Availability

ADI says its ADF4156 is available now in two package options. You can order an LFCSP (lead-frame chip-scale package) or a TSSOP (thin shrink small-outline package). The IC is priced at about $3.50 each, in quantities of 1000. However, note there is no datasheet on ADI's Web site for this IC at this time.

The ADF4002 is also available now in both LFCSP and TSSOP packages. It's priced at less than about $2 per unit, in quantities of 1000.

Click here for an ADF4002 datasheet (in Adobe Acrobat .PDF format). There is no datahseet for the ADF4156 on ADI's Web site at this time.

For more information, contact Analog Devices, Inc., 804 Woburn St., Wilmington, Mass. 01887. Phone: 800-ANALOGD (800-262-5643) or 781-937-1428. Fax: 781-937-1021.

Analog Devices , 800-262-5643, www.analog.com

0 comments on “Freebie PLL design tool debuts with PLL hardware

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.